/* SPDX-License-Identifier: GPL-2.0-only */ /* * ispreg.h * * TI OMAP3 ISP - Registers definitions * * Copyright (C) 2010 Nokia Corporation * Copyright (C) 2009 Texas Instruments, Inc * * Contacts: Laurent Pinchart <[email protected]> * Sakari Ailus <[email protected]> */ #ifndef OMAP3_ISP_REG_H #define OMAP3_ISP_REG_H #define CM_CAM_MCLK_HZ … /* ISP module register offset */ #define ISP_REVISION … #define ISP_SYSCONFIG … #define ISP_SYSSTATUS … #define ISP_IRQ0ENABLE … #define ISP_IRQ0STATUS … #define ISP_IRQ1ENABLE … #define ISP_IRQ1STATUS … #define ISP_TCTRL_GRESET_LENGTH … #define ISP_TCTRL_PSTRB_REPLAY … #define ISP_CTRL … #define ISP_SECURE … #define ISP_TCTRL_CTRL … #define ISP_TCTRL_FRAME … #define ISP_TCTRL_PSTRB_DELAY … #define ISP_TCTRL_STRB_DELAY … #define ISP_TCTRL_SHUT_DELAY … #define ISP_TCTRL_PSTRB_LENGTH … #define ISP_TCTRL_STRB_LENGTH … #define ISP_TCTRL_SHUT_LENGTH … #define ISP_PING_PONG_ADDR … #define ISP_PING_PONG_MEM_RANGE … #define ISP_PING_PONG_BUF_SIZE … /* CCP2 receiver registers */ #define ISPCCP2_REVISION … #define ISPCCP2_SYSCONFIG … #define ISPCCP2_SYSCONFIG_SOFT_RESET … #define ISPCCP2_SYSCONFIG_AUTO_IDLE … #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT … #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE … #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_NO … #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART … #define ISPCCP2_SYSSTATUS … #define ISPCCP2_SYSSTATUS_RESET_DONE … #define ISPCCP2_LC01_IRQENABLE … #define ISPCCP2_LC01_IRQSTATUS … #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ … #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ … #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ … #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ … #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ … #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ … #define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ … #define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ … #define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ … #define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ … #define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ … #define ISPCCP2_LC23_IRQENABLE … #define ISPCCP2_LC23_IRQSTATUS … #define ISPCCP2_LCM_IRQENABLE … #define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ … #define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ … #define ISPCCP2_LCM_IRQSTATUS … #define ISPCCP2_CTRL … #define ISPCCP2_CTRL_IF_EN … #define ISPCCP2_CTRL_PHY_SEL … #define ISPCCP2_CTRL_PHY_SEL_CLOCK … #define ISPCCP2_CTRL_PHY_SEL_STROBE … #define ISPCCP2_CTRL_PHY_SEL_MASK … #define ISPCCP2_CTRL_PHY_SEL_SHIFT … #define ISPCCP2_CTRL_IO_OUT_SEL … #define ISPCCP2_CTRL_IO_OUT_SEL_MASK … #define ISPCCP2_CTRL_IO_OUT_SEL_SHIFT … #define ISPCCP2_CTRL_MODE … #define ISPCCP2_CTRL_VP_CLK_FORCE_ON … #define ISPCCP2_CTRL_INV … #define ISPCCP2_CTRL_INV_MASK … #define ISPCCP2_CTRL_INV_SHIFT … #define ISPCCP2_CTRL_VP_ONLY_EN … #define ISPCCP2_CTRL_VP_CLK_POL … #define ISPCCP2_CTRL_VP_CLK_POL_MASK … #define ISPCCP2_CTRL_VP_CLK_POL_SHIFT … #define ISPCCP2_CTRL_VPCLK_DIV_SHIFT … #define ISPCCP2_CTRL_VPCLK_DIV_MASK … #define ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT … #define ISPCCP2_CTRL_VP_OUT_CTRL_MASK … #define ISPCCP2_DBG … #define ISPCCP2_GNQ … #define ISPCCP2_LCx_CTRL(x) … #define ISPCCP2_LCx_CTRL_CHAN_EN … #define ISPCCP2_LCx_CTRL_CRC_EN … #define ISPCCP2_LCx_CTRL_CRC_MASK … #define ISPCCP2_LCx_CTRL_CRC_SHIFT … #define ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0 … #define ISPCCP2_LCx_CTRL_REGION_EN … #define ISPCCP2_LCx_CTRL_REGION_MASK … #define ISPCCP2_LCx_CTRL_REGION_SHIFT … #define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0 … #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0 … #define ISPCCP2_LCx_CTRL_FORMAT_MASK … #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT … #define ISPCCP2_LCx_CODE(x) … #define ISPCCP2_LCx_STAT_START(x) … #define ISPCCP2_LCx_STAT_SIZE(x) … #define ISPCCP2_LCx_SOF_ADDR(x) … #define ISPCCP2_LCx_EOF_ADDR(x) … #define ISPCCP2_LCx_DAT_START(x) … #define ISPCCP2_LCx_DAT_SIZE(x) … #define ISPCCP2_LCx_DAT_MASK … #define ISPCCP2_LCx_DAT_SHIFT … #define ISPCCP2_LCx_DAT_PING_ADDR(x) … #define ISPCCP2_LCx_DAT_PONG_ADDR(x) … #define ISPCCP2_LCx_DAT_OFST(x) … #define ISPCCP2_LCM_CTRL … #define ISPCCP2_LCM_CTRL_CHAN_EN … #define ISPCCP2_LCM_CTRL_DST_PORT … #define ISPCCP2_LCM_CTRL_DST_PORT_SHIFT … #define ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT … #define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK … #define ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT … #define ISPCCP2_LCM_CTRL_BURST_SIZE_MASK … #define ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT … #define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK … #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT … #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK … #define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED … #define ISPCCP2_LCM_CTRL_SRC_PACK … #define ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT … #define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK … #define ISPCCP2_LCM_VSIZE … #define ISPCCP2_LCM_VSIZE_SHIFT … #define ISPCCP2_LCM_HSIZE … #define ISPCCP2_LCM_HSIZE_SHIFT … #define ISPCCP2_LCM_PREFETCH … #define ISPCCP2_LCM_PREFETCH_SHIFT … #define ISPCCP2_LCM_SRC_ADDR … #define ISPCCP2_LCM_SRC_OFST … #define ISPCCP2_LCM_DST_ADDR … #define ISPCCP2_LCM_DST_OFST … /* CCDC module register offset */ #define ISPCCDC_PID … #define ISPCCDC_PCR … #define ISPCCDC_SYN_MODE … #define ISPCCDC_HD_VD_WID … #define ISPCCDC_PIX_LINES … #define ISPCCDC_HORZ_INFO … #define ISPCCDC_VERT_START … #define ISPCCDC_VERT_LINES … #define ISPCCDC_CULLING … #define ISPCCDC_HSIZE_OFF … #define ISPCCDC_SDOFST … #define ISPCCDC_SDR_ADDR … #define ISPCCDC_CLAMP … #define ISPCCDC_DCSUB … #define ISPCCDC_COLPTN … #define ISPCCDC_BLKCMP … #define ISPCCDC_FPC … #define ISPCCDC_FPC_ADDR … #define ISPCCDC_VDINT … #define ISPCCDC_ALAW … #define ISPCCDC_REC656IF … #define ISPCCDC_CFG … #define ISPCCDC_FMTCFG … #define ISPCCDC_FMT_HORZ … #define ISPCCDC_FMT_VERT … #define ISPCCDC_FMT_ADDR0 … #define ISPCCDC_FMT_ADDR1 … #define ISPCCDC_FMT_ADDR2 … #define ISPCCDC_FMT_ADDR3 … #define ISPCCDC_FMT_ADDR4 … #define ISPCCDC_FMT_ADDR5 … #define ISPCCDC_FMT_ADDR6 … #define ISPCCDC_FMT_ADDR7 … #define ISPCCDC_PRGEVEN0 … #define ISPCCDC_PRGEVEN1 … #define ISPCCDC_PRGODD0 … #define ISPCCDC_PRGODD1 … #define ISPCCDC_VP_OUT … #define ISPCCDC_LSC_CONFIG … #define ISPCCDC_LSC_INITIAL … #define ISPCCDC_LSC_TABLE_BASE … #define ISPCCDC_LSC_TABLE_OFFSET … /* SBL */ #define ISPSBL_PCR … #define ISPSBL_PCR_H3A_AEAWB_WBL_OVF … #define ISPSBL_PCR_H3A_AF_WBL_OVF … #define ISPSBL_PCR_RSZ4_WBL_OVF … #define ISPSBL_PCR_RSZ3_WBL_OVF … #define ISPSBL_PCR_RSZ2_WBL_OVF … #define ISPSBL_PCR_RSZ1_WBL_OVF … #define ISPSBL_PCR_PRV_WBL_OVF … #define ISPSBL_PCR_CCDC_WBL_OVF … #define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF … #define ISPSBL_PCR_CSIA_WBL_OVF … #define ISPSBL_PCR_CSIB_WBL_OVF … #define ISPSBL_CCDC_WR_0 … #define ISPSBL_CCDC_WR_0_DATA_READY … #define ISPSBL_CCDC_WR_1 … #define ISPSBL_CCDC_WR_2 … #define ISPSBL_CCDC_WR_3 … #define ISPSBL_SDR_REQ_EXP … #define ISPSBL_SDR_REQ_HIST_EXP_SHIFT … #define ISPSBL_SDR_REQ_HIST_EXP_MASK … #define ISPSBL_SDR_REQ_RSZ_EXP_SHIFT … #define ISPSBL_SDR_REQ_RSZ_EXP_MASK … #define ISPSBL_SDR_REQ_PRV_EXP_SHIFT … #define ISPSBL_SDR_REQ_PRV_EXP_MASK … /* Histogram registers */ #define ISPHIST_PID … #define ISPHIST_PCR … #define ISPHIST_CNT … #define ISPHIST_WB_GAIN … #define ISPHIST_R0_HORZ … #define ISPHIST_R0_VERT … #define ISPHIST_R1_HORZ … #define ISPHIST_R1_VERT … #define ISPHIST_R2_HORZ … #define ISPHIST_R2_VERT … #define ISPHIST_R3_HORZ … #define ISPHIST_R3_VERT … #define ISPHIST_ADDR … #define ISPHIST_DATA … #define ISPHIST_RADD … #define ISPHIST_RADD_OFF … #define ISPHIST_H_V_INFO … /* H3A module registers */ #define ISPH3A_PID … #define ISPH3A_PCR … #define ISPH3A_AEWWIN1 … #define ISPH3A_AEWINSTART … #define ISPH3A_AEWINBLK … #define ISPH3A_AEWSUBWIN … #define ISPH3A_AEWBUFST … #define ISPH3A_AFPAX1 … #define ISPH3A_AFPAX2 … #define ISPH3A_AFPAXSTART … #define ISPH3A_AFIIRSH … #define ISPH3A_AFBUFST … #define ISPH3A_AFCOEF010 … #define ISPH3A_AFCOEF032 … #define ISPH3A_AFCOEF054 … #define ISPH3A_AFCOEF076 … #define ISPH3A_AFCOEF098 … #define ISPH3A_AFCOEF0010 … #define ISPH3A_AFCOEF110 … #define ISPH3A_AFCOEF132 … #define ISPH3A_AFCOEF154 … #define ISPH3A_AFCOEF176 … #define ISPH3A_AFCOEF198 … #define ISPH3A_AFCOEF1010 … #define ISPPRV_PCR … #define ISPPRV_HORZ_INFO … #define ISPPRV_VERT_INFO … #define ISPPRV_RSDR_ADDR … #define ISPPRV_RADR_OFFSET … #define ISPPRV_DSDR_ADDR … #define ISPPRV_DRKF_OFFSET … #define ISPPRV_WSDR_ADDR … #define ISPPRV_WADD_OFFSET … #define ISPPRV_AVE … #define ISPPRV_HMED … #define ISPPRV_NF … #define ISPPRV_WB_DGAIN … #define ISPPRV_WBGAIN … #define ISPPRV_WBSEL … #define ISPPRV_CFA … #define ISPPRV_BLKADJOFF … #define ISPPRV_RGB_MAT1 … #define ISPPRV_RGB_MAT2 … #define ISPPRV_RGB_MAT3 … #define ISPPRV_RGB_MAT4 … #define ISPPRV_RGB_MAT5 … #define ISPPRV_RGB_OFF1 … #define ISPPRV_RGB_OFF2 … #define ISPPRV_CSC0 … #define ISPPRV_CSC1 … #define ISPPRV_CSC2 … #define ISPPRV_CSC_OFFSET … #define ISPPRV_CNT_BRT … #define ISPPRV_CSUP … #define ISPPRV_SETUP_YC … #define ISPPRV_SET_TBL_ADDR … #define ISPPRV_SET_TBL_DATA … #define ISPPRV_CDC_THR0 … #define ISPPRV_CDC_THR1 … #define ISPPRV_CDC_THR2 … #define ISPPRV_CDC_THR3 … #define ISPPRV_REDGAMMA_TABLE_ADDR … #define ISPPRV_GREENGAMMA_TABLE_ADDR … #define ISPPRV_BLUEGAMMA_TABLE_ADDR … #define ISPPRV_NF_TABLE_ADDR … #define ISPPRV_YENH_TABLE_ADDR … #define ISPPRV_CFA_TABLE_ADDR … #define ISPRSZ_MIN_OUTPUT … #define ISPRSZ_MAX_OUTPUT … /* Resizer module register offset */ #define ISPRSZ_PID … #define ISPRSZ_PCR … #define ISPRSZ_CNT … #define ISPRSZ_OUT_SIZE … #define ISPRSZ_IN_START … #define ISPRSZ_IN_SIZE … #define ISPRSZ_SDR_INADD … #define ISPRSZ_SDR_INOFF … #define ISPRSZ_SDR_OUTADD … #define ISPRSZ_SDR_OUTOFF … #define ISPRSZ_HFILT10 … #define ISPRSZ_HFILT32 … #define ISPRSZ_HFILT54 … #define ISPRSZ_HFILT76 … #define ISPRSZ_HFILT98 … #define ISPRSZ_HFILT1110 … #define ISPRSZ_HFILT1312 … #define ISPRSZ_HFILT1514 … #define ISPRSZ_HFILT1716 … #define ISPRSZ_HFILT1918 … #define ISPRSZ_HFILT2120 … #define ISPRSZ_HFILT2322 … #define ISPRSZ_HFILT2524 … #define ISPRSZ_HFILT2726 … #define ISPRSZ_HFILT2928 … #define ISPRSZ_HFILT3130 … #define ISPRSZ_VFILT10 … #define ISPRSZ_VFILT32 … #define ISPRSZ_VFILT54 … #define ISPRSZ_VFILT76 … #define ISPRSZ_VFILT98 … #define ISPRSZ_VFILT1110 … #define ISPRSZ_VFILT1312 … #define ISPRSZ_VFILT1514 … #define ISPRSZ_VFILT1716 … #define ISPRSZ_VFILT1918 … #define ISPRSZ_VFILT2120 … #define ISPRSZ_VFILT2322 … #define ISPRSZ_VFILT2524 … #define ISPRSZ_VFILT2726 … #define ISPRSZ_VFILT2928 … #define ISPRSZ_VFILT3130 … #define ISPRSZ_YENH … #define ISP_INT_CLR … #define ISPPRV_PCR_EN … #define ISPPRV_PCR_BUSY … #define ISPPRV_PCR_SOURCE … #define ISPPRV_PCR_ONESHOT … #define ISPPRV_PCR_WIDTH … #define ISPPRV_PCR_INVALAW … #define ISPPRV_PCR_DRKFEN … #define ISPPRV_PCR_DRKFCAP … #define ISPPRV_PCR_HMEDEN … #define ISPPRV_PCR_NFEN … #define ISPPRV_PCR_CFAEN … #define ISPPRV_PCR_CFAFMT_SHIFT … #define ISPPRV_PCR_CFAFMT_MASK … #define ISPPRV_PCR_CFAFMT_BAYER … #define ISPPRV_PCR_CFAFMT_SONYVGA … #define ISPPRV_PCR_CFAFMT_RGBFOVEON … #define ISPPRV_PCR_CFAFMT_DNSPL … #define ISPPRV_PCR_CFAFMT_HONEYCOMB … #define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON … #define ISPPRV_PCR_YNENHEN … #define ISPPRV_PCR_SUPEN … #define ISPPRV_PCR_YCPOS_SHIFT … #define ISPPRV_PCR_YCPOS_YCrYCb … #define ISPPRV_PCR_YCPOS_YCbYCr … #define ISPPRV_PCR_YCPOS_CbYCrY … #define ISPPRV_PCR_YCPOS_CrYCbY … #define ISPPRV_PCR_RSZPORT … #define ISPPRV_PCR_SDRPORT … #define ISPPRV_PCR_SCOMP_EN … #define ISPPRV_PCR_SCOMP_SFT_SHIFT … #define ISPPRV_PCR_SCOMP_SFT_MASK … #define ISPPRV_PCR_GAMMA_BYPASS … #define ISPPRV_PCR_DCOREN … #define ISPPRV_PCR_DCCOUP … #define ISPPRV_PCR_DRK_FAIL … #define ISPPRV_HORZ_INFO_EPH_SHIFT … #define ISPPRV_HORZ_INFO_EPH_MASK … #define ISPPRV_HORZ_INFO_SPH_SHIFT … #define ISPPRV_HORZ_INFO_SPH_MASK … #define ISPPRV_VERT_INFO_ELV_SHIFT … #define ISPPRV_VERT_INFO_ELV_MASK … #define ISPPRV_VERT_INFO_SLV_SHIFT … #define ISPPRV_VERT_INFO_SLV_MASK … #define ISPPRV_AVE_EVENDIST_SHIFT … #define ISPPRV_AVE_EVENDIST_1 … #define ISPPRV_AVE_EVENDIST_2 … #define ISPPRV_AVE_EVENDIST_3 … #define ISPPRV_AVE_EVENDIST_4 … #define ISPPRV_AVE_ODDDIST_SHIFT … #define ISPPRV_AVE_ODDDIST_1 … #define ISPPRV_AVE_ODDDIST_2 … #define ISPPRV_AVE_ODDDIST_3 … #define ISPPRV_AVE_ODDDIST_4 … #define ISPPRV_HMED_THRESHOLD_SHIFT … #define ISPPRV_HMED_EVENDIST … #define ISPPRV_HMED_ODDDIST … #define ISPPRV_WBGAIN_COEF0_SHIFT … #define ISPPRV_WBGAIN_COEF1_SHIFT … #define ISPPRV_WBGAIN_COEF2_SHIFT … #define ISPPRV_WBGAIN_COEF3_SHIFT … #define ISPPRV_WBSEL_COEF0 … #define ISPPRV_WBSEL_COEF1 … #define ISPPRV_WBSEL_COEF2 … #define ISPPRV_WBSEL_COEF3 … #define ISPPRV_WBSEL_N0_0_SHIFT … #define ISPPRV_WBSEL_N0_1_SHIFT … #define ISPPRV_WBSEL_N0_2_SHIFT … #define ISPPRV_WBSEL_N0_3_SHIFT … #define ISPPRV_WBSEL_N1_0_SHIFT … #define ISPPRV_WBSEL_N1_1_SHIFT … #define ISPPRV_WBSEL_N1_2_SHIFT … #define ISPPRV_WBSEL_N1_3_SHIFT … #define ISPPRV_WBSEL_N2_0_SHIFT … #define ISPPRV_WBSEL_N2_1_SHIFT … #define ISPPRV_WBSEL_N2_2_SHIFT … #define ISPPRV_WBSEL_N2_3_SHIFT … #define ISPPRV_WBSEL_N3_0_SHIFT … #define ISPPRV_WBSEL_N3_1_SHIFT … #define ISPPRV_WBSEL_N3_2_SHIFT … #define ISPPRV_WBSEL_N3_3_SHIFT … #define ISPPRV_CFA_GRADTH_HOR_SHIFT … #define ISPPRV_CFA_GRADTH_VER_SHIFT … #define ISPPRV_BLKADJOFF_B_SHIFT … #define ISPPRV_BLKADJOFF_G_SHIFT … #define ISPPRV_BLKADJOFF_R_SHIFT … #define ISPPRV_RGB_MAT1_MTX_RR_SHIFT … #define ISPPRV_RGB_MAT1_MTX_GR_SHIFT … #define ISPPRV_RGB_MAT2_MTX_BR_SHIFT … #define ISPPRV_RGB_MAT2_MTX_RG_SHIFT … #define ISPPRV_RGB_MAT3_MTX_GG_SHIFT … #define ISPPRV_RGB_MAT3_MTX_BG_SHIFT … #define ISPPRV_RGB_MAT4_MTX_RB_SHIFT … #define ISPPRV_RGB_MAT4_MTX_GB_SHIFT … #define ISPPRV_RGB_MAT5_MTX_BB_SHIFT … #define ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT … #define ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT … #define ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT … #define ISPPRV_CSC0_RY_SHIFT … #define ISPPRV_CSC0_GY_SHIFT … #define ISPPRV_CSC0_BY_SHIFT … #define ISPPRV_CSC1_RCB_SHIFT … #define ISPPRV_CSC1_GCB_SHIFT … #define ISPPRV_CSC1_BCB_SHIFT … #define ISPPRV_CSC2_RCR_SHIFT … #define ISPPRV_CSC2_GCR_SHIFT … #define ISPPRV_CSC2_BCR_SHIFT … #define ISPPRV_CSC_OFFSET_CR_SHIFT … #define ISPPRV_CSC_OFFSET_CB_SHIFT … #define ISPPRV_CSC_OFFSET_Y_SHIFT … #define ISPPRV_CNT_BRT_BRT_SHIFT … #define ISPPRV_CNT_BRT_CNT_SHIFT … #define ISPPRV_CONTRAST_MAX … #define ISPPRV_CONTRAST_MIN … #define ISPPRV_BRIGHT_MIN … #define ISPPRV_BRIGHT_MAX … #define ISPPRV_CSUP_CSUPG_SHIFT … #define ISPPRV_CSUP_THRES_SHIFT … #define ISPPRV_CSUP_HPYF_SHIFT … #define ISPPRV_SETUP_YC_MINC_SHIFT … #define ISPPRV_SETUP_YC_MAXC_SHIFT … #define ISPPRV_SETUP_YC_MINY_SHIFT … #define ISPPRV_SETUP_YC_MAXY_SHIFT … #define ISPPRV_YC_MAX … #define ISPPRV_YC_MIN … /* Define bit fields within selected registers */ #define ISP_REVISION_SHIFT … #define ISP_SYSCONFIG_AUTOIDLE … #define ISP_SYSCONFIG_SOFTRESET … #define ISP_SYSCONFIG_MIDLEMODE_SHIFT … #define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY … #define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY … #define ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY … #define ISP_SYSSTATUS_RESETDONE … #define IRQ0ENABLE_CSIA_IRQ … #define IRQ0ENABLE_CSIC_IRQ … #define IRQ0ENABLE_CCP2_LCM_IRQ … #define IRQ0ENABLE_CCP2_LC0_IRQ … #define IRQ0ENABLE_CCP2_LC1_IRQ … #define IRQ0ENABLE_CCP2_LC2_IRQ … #define IRQ0ENABLE_CCP2_LC3_IRQ … #define IRQ0ENABLE_CSIB_IRQ … #define IRQ0ENABLE_CCDC_VD0_IRQ … #define IRQ0ENABLE_CCDC_VD1_IRQ … #define IRQ0ENABLE_CCDC_VD2_IRQ … #define IRQ0ENABLE_CCDC_ERR_IRQ … #define IRQ0ENABLE_H3A_AF_DONE_IRQ … #define IRQ0ENABLE_H3A_AWB_DONE_IRQ … #define IRQ0ENABLE_HIST_DONE_IRQ … #define IRQ0ENABLE_CCDC_LSC_DONE_IRQ … #define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ … #define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ … #define IRQ0ENABLE_PRV_DONE_IRQ … #define IRQ0ENABLE_RSZ_DONE_IRQ … #define IRQ0ENABLE_OVF_IRQ … #define IRQ0ENABLE_PING_IRQ … #define IRQ0ENABLE_PONG_IRQ … #define IRQ0ENABLE_MMU_ERR_IRQ … #define IRQ0ENABLE_OCP_ERR_IRQ … #define IRQ0ENABLE_SEC_ERR_IRQ … #define IRQ0ENABLE_HS_VS_IRQ … #define IRQ0STATUS_CSIA_IRQ … #define IRQ0STATUS_CSI2C_IRQ … #define IRQ0STATUS_CCP2_LCM_IRQ … #define IRQ0STATUS_CCP2_LC0_IRQ … #define IRQ0STATUS_CSIB_IRQ … #define IRQ0STATUS_CSIB_LC1_IRQ … #define IRQ0STATUS_CSIB_LC2_IRQ … #define IRQ0STATUS_CSIB_LC3_IRQ … #define IRQ0STATUS_CCDC_VD0_IRQ … #define IRQ0STATUS_CCDC_VD1_IRQ … #define IRQ0STATUS_CCDC_VD2_IRQ … #define IRQ0STATUS_CCDC_ERR_IRQ … #define IRQ0STATUS_H3A_AF_DONE_IRQ … #define IRQ0STATUS_H3A_AWB_DONE_IRQ … #define IRQ0STATUS_HIST_DONE_IRQ … #define IRQ0STATUS_CCDC_LSC_DONE_IRQ … #define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ … #define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ … #define IRQ0STATUS_PRV_DONE_IRQ … #define IRQ0STATUS_RSZ_DONE_IRQ … #define IRQ0STATUS_OVF_IRQ … #define IRQ0STATUS_PING_IRQ … #define IRQ0STATUS_PONG_IRQ … #define IRQ0STATUS_MMU_ERR_IRQ … #define IRQ0STATUS_OCP_ERR_IRQ … #define IRQ0STATUS_SEC_ERR_IRQ … #define IRQ0STATUS_HS_VS_IRQ … #define TCTRL_GRESET_LEN … #define TCTRL_PSTRB_REPLAY_DELAY … #define TCTRL_PSTRB_REPLAY_COUNTER_SHIFT … #define ISPCTRL_PAR_SER_CLK_SEL_PARALLEL … #define ISPCTRL_PAR_SER_CLK_SEL_CSIA … #define ISPCTRL_PAR_SER_CLK_SEL_CSIB … #define ISPCTRL_PAR_SER_CLK_SEL_CSIC … #define ISPCTRL_PAR_SER_CLK_SEL_MASK … #define ISPCTRL_PAR_BRIDGE_SHIFT … #define ISPCTRL_PAR_BRIDGE_DISABLE … #define ISPCTRL_PAR_BRIDGE_LENDIAN … #define ISPCTRL_PAR_BRIDGE_BENDIAN … #define ISPCTRL_PAR_BRIDGE_MASK … #define ISPCTRL_PAR_CLK_POL_SHIFT … #define ISPCTRL_PAR_CLK_POL_INV … #define ISPCTRL_PING_PONG_EN … #define ISPCTRL_SHIFT_SHIFT … #define ISPCTRL_SHIFT_0 … #define ISPCTRL_SHIFT_2 … #define ISPCTRL_SHIFT_4 … #define ISPCTRL_SHIFT_MASK … #define ISPCTRL_CCDC_CLK_EN … #define ISPCTRL_SCMP_CLK_EN … #define ISPCTRL_H3A_CLK_EN … #define ISPCTRL_HIST_CLK_EN … #define ISPCTRL_PREV_CLK_EN … #define ISPCTRL_RSZ_CLK_EN … #define ISPCTRL_SYNC_DETECT_SHIFT … #define ISPCTRL_SYNC_DETECT_HSFALL … #define ISPCTRL_SYNC_DETECT_HSRISE … #define ISPCTRL_SYNC_DETECT_VSFALL … #define ISPCTRL_SYNC_DETECT_VSRISE … #define ISPCTRL_SYNC_DETECT_MASK … #define ISPCTRL_CCDC_RAM_EN … #define ISPCTRL_PREV_RAM_EN … #define ISPCTRL_SBL_RD_RAM_EN … #define ISPCTRL_SBL_WR1_RAM_EN … #define ISPCTRL_SBL_WR0_RAM_EN … #define ISPCTRL_SBL_AUTOIDLE … #define ISPCTRL_SBL_SHARED_WPORTC … #define ISPCTRL_SBL_SHARED_RPORTA … #define ISPCTRL_SBL_SHARED_RPORTB … #define ISPCTRL_JPEG_FLUSH … #define ISPCTRL_CCDC_FLUSH … #define ISPSECURE_SECUREMODE … #define ISPTCTRL_CTRL_DIV_LOW … #define ISPTCTRL_CTRL_DIV_HIGH … #define ISPTCTRL_CTRL_DIV_BYPASS … #define ISPTCTRL_CTRL_DIVA_SHIFT … #define ISPTCTRL_CTRL_DIVA_MASK … #define ISPTCTRL_CTRL_DIVB_SHIFT … #define ISPTCTRL_CTRL_DIVB_MASK … #define ISPTCTRL_CTRL_DIVC_SHIFT … #define ISPTCTRL_CTRL_DIVC_NOCLOCK … #define ISPTCTRL_CTRL_SHUTEN … #define ISPTCTRL_CTRL_PSTRBEN … #define ISPTCTRL_CTRL_STRBEN … #define ISPTCTRL_CTRL_SHUTPOL … #define ISPTCTRL_CTRL_STRBPSTRBPOL … #define ISPTCTRL_CTRL_INSEL_SHIFT … #define ISPTCTRL_CTRL_INSEL_PARALLEL … #define ISPTCTRL_CTRL_INSEL_CSIA … #define ISPTCTRL_CTRL_INSEL_CSIB … #define ISPTCTRL_CTRL_GRESETEn … #define ISPTCTRL_CTRL_GRESETPOL … #define ISPTCTRL_CTRL_GRESETDIR … #define ISPTCTRL_FRAME_SHUT_SHIFT … #define ISPTCTRL_FRAME_PSTRB_SHIFT … #define ISPTCTRL_FRAME_STRB_SHIFT … #define ISPCCDC_PID_PREV_SHIFT … #define ISPCCDC_PID_CID_SHIFT … #define ISPCCDC_PID_TID_SHIFT … #define ISPCCDC_PCR_EN … #define ISPCCDC_PCR_BUSY … #define ISPCCDC_SYN_MODE_VDHDOUT … #define ISPCCDC_SYN_MODE_FLDOUT … #define ISPCCDC_SYN_MODE_VDPOL … #define ISPCCDC_SYN_MODE_HDPOL … #define ISPCCDC_SYN_MODE_FLDPOL … #define ISPCCDC_SYN_MODE_EXWEN … #define ISPCCDC_SYN_MODE_DATAPOL … #define ISPCCDC_SYN_MODE_FLDMODE … #define ISPCCDC_SYN_MODE_DATSIZ_MASK … #define ISPCCDC_SYN_MODE_DATSIZ_8_16 … #define ISPCCDC_SYN_MODE_DATSIZ_12 … #define ISPCCDC_SYN_MODE_DATSIZ_11 … #define ISPCCDC_SYN_MODE_DATSIZ_10 … #define ISPCCDC_SYN_MODE_DATSIZ_8 … #define ISPCCDC_SYN_MODE_PACK8 … #define ISPCCDC_SYN_MODE_INPMOD_MASK … #define ISPCCDC_SYN_MODE_INPMOD_RAW … #define ISPCCDC_SYN_MODE_INPMOD_YCBCR16 … #define ISPCCDC_SYN_MODE_INPMOD_YCBCR8 … #define ISPCCDC_SYN_MODE_LPF … #define ISPCCDC_SYN_MODE_FLDSTAT … #define ISPCCDC_SYN_MODE_VDHDEN … #define ISPCCDC_SYN_MODE_WEN … #define ISPCCDC_SYN_MODE_VP2SDR … #define ISPCCDC_SYN_MODE_SDR2RSZ … #define ISPCCDC_HD_VD_WID_VDW_SHIFT … #define ISPCCDC_HD_VD_WID_HDW_SHIFT … #define ISPCCDC_PIX_LINES_HLPRF_SHIFT … #define ISPCCDC_PIX_LINES_PPLN_SHIFT … #define ISPCCDC_HORZ_INFO_NPH_SHIFT … #define ISPCCDC_HORZ_INFO_NPH_MASK … #define ISPCCDC_HORZ_INFO_SPH_SHIFT … #define ISPCCDC_HORZ_INFO_SPH_MASK … #define ISPCCDC_VERT_START_SLV1_SHIFT … #define ISPCCDC_VERT_START_SLV0_SHIFT … #define ISPCCDC_VERT_START_SLV0_MASK … #define ISPCCDC_VERT_LINES_NLV_SHIFT … #define ISPCCDC_VERT_LINES_NLV_MASK … #define ISPCCDC_CULLING_CULV_SHIFT … #define ISPCCDC_CULLING_CULHODD_SHIFT … #define ISPCCDC_CULLING_CULHEVN_SHIFT … #define ISPCCDC_HSIZE_OFF_SHIFT … #define ISPCCDC_SDOFST_FIINV … #define ISPCCDC_SDOFST_FOFST_SHIFT … #define ISPCCDC_SDOFST_FOFST_MASK … #define ISPCCDC_SDOFST_LOFST3_SHIFT … #define ISPCCDC_SDOFST_LOFST2_SHIFT … #define ISPCCDC_SDOFST_LOFST1_SHIFT … #define ISPCCDC_SDOFST_LOFST0_SHIFT … #define ISPCCDC_CLAMP_OBGAIN_SHIFT … #define ISPCCDC_CLAMP_OBST_SHIFT … #define ISPCCDC_CLAMP_OBSLN_SHIFT … #define ISPCCDC_CLAMP_OBSLEN_SHIFT … #define ISPCCDC_CLAMP_CLAMPEN … #define ISPCCDC_COLPTN_R_Ye … #define ISPCCDC_COLPTN_Gr_Cy … #define ISPCCDC_COLPTN_Gb_G … #define ISPCCDC_COLPTN_B_Mg … #define ISPCCDC_COLPTN_CP0PLC0_SHIFT … #define ISPCCDC_COLPTN_CP0PLC1_SHIFT … #define ISPCCDC_COLPTN_CP0PLC2_SHIFT … #define ISPCCDC_COLPTN_CP0PLC3_SHIFT … #define ISPCCDC_COLPTN_CP1PLC0_SHIFT … #define ISPCCDC_COLPTN_CP1PLC1_SHIFT … #define ISPCCDC_COLPTN_CP1PLC2_SHIFT … #define ISPCCDC_COLPTN_CP1PLC3_SHIFT … #define ISPCCDC_COLPTN_CP2PLC0_SHIFT … #define ISPCCDC_COLPTN_CP2PLC1_SHIFT … #define ISPCCDC_COLPTN_CP2PLC2_SHIFT … #define ISPCCDC_COLPTN_CP2PLC3_SHIFT … #define ISPCCDC_COLPTN_CP3PLC0_SHIFT … #define ISPCCDC_COLPTN_CP3PLC1_SHIFT … #define ISPCCDC_COLPTN_CP3PLC2_SHIFT … #define ISPCCDC_COLPTN_CP3PLC3_SHIFT … #define ISPCCDC_BLKCMP_B_MG_SHIFT … #define ISPCCDC_BLKCMP_GB_G_SHIFT … #define ISPCCDC_BLKCMP_GR_CY_SHIFT … #define ISPCCDC_BLKCMP_R_YE_SHIFT … #define ISPCCDC_FPC_FPNUM_SHIFT … #define ISPCCDC_FPC_FPCEN … #define ISPCCDC_FPC_FPERR … #define ISPCCDC_VDINT_1_SHIFT … #define ISPCCDC_VDINT_1_MASK … #define ISPCCDC_VDINT_0_SHIFT … #define ISPCCDC_VDINT_0_MASK … #define ISPCCDC_ALAW_GWDI_12_3 … #define ISPCCDC_ALAW_GWDI_11_2 … #define ISPCCDC_ALAW_GWDI_10_1 … #define ISPCCDC_ALAW_GWDI_9_0 … #define ISPCCDC_ALAW_CCDTBL … #define ISPCCDC_REC656IF_R656ON … #define ISPCCDC_REC656IF_ECCFVH … #define ISPCCDC_CFG_BW656 … #define ISPCCDC_CFG_FIDMD_SHIFT … #define ISPCCDC_CFG_WENLOG … #define ISPCCDC_CFG_WENLOG_AND … #define ISPCCDC_CFG_WENLOG_OR … #define ISPCCDC_CFG_Y8POS … #define ISPCCDC_CFG_BSWD … #define ISPCCDC_CFG_MSBINVI … #define ISPCCDC_CFG_VDLC … #define ISPCCDC_FMTCFG_FMTEN … #define ISPCCDC_FMTCFG_LNALT … #define ISPCCDC_FMTCFG_LNUM_SHIFT … #define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT … #define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT … #define ISPCCDC_FMTCFG_VPIN_MASK … #define ISPCCDC_FMTCFG_VPIN_12_3 … #define ISPCCDC_FMTCFG_VPIN_11_2 … #define ISPCCDC_FMTCFG_VPIN_10_1 … #define ISPCCDC_FMTCFG_VPIN_9_0 … #define ISPCCDC_FMTCFG_VPEN … #define ISPCCDC_FMTCFG_VPIF_FRQ_MASK … #define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT … #define ISPCCDC_FMTCFG_VPIF_FRQ_BY2 … #define ISPCCDC_FMTCFG_VPIF_FRQ_BY3 … #define ISPCCDC_FMTCFG_VPIF_FRQ_BY4 … #define ISPCCDC_FMTCFG_VPIF_FRQ_BY5 … #define ISPCCDC_FMTCFG_VPIF_FRQ_BY6 … #define ISPCCDC_FMT_HORZ_FMTLNH_SHIFT … #define ISPCCDC_FMT_HORZ_FMTSPH_SHIFT … #define ISPCCDC_FMT_VERT_FMTLNV_SHIFT … #define ISPCCDC_FMT_VERT_FMTSLV_SHIFT … #define ISPCCDC_FMT_HORZ_FMTSPH_MASK … #define ISPCCDC_FMT_HORZ_FMTLNH_MASK … #define ISPCCDC_FMT_VERT_FMTSLV_MASK … #define ISPCCDC_FMT_VERT_FMTLNV_MASK … #define ISPCCDC_VP_OUT_HORZ_ST_SHIFT … #define ISPCCDC_VP_OUT_HORZ_NUM_SHIFT … #define ISPCCDC_VP_OUT_VERT_NUM_SHIFT … #define ISPRSZ_PID_PREV_SHIFT … #define ISPRSZ_PID_CID_SHIFT … #define ISPRSZ_PID_TID_SHIFT … #define ISPRSZ_PCR_ENABLE … #define ISPRSZ_PCR_BUSY … #define ISPRSZ_PCR_ONESHOT … #define ISPRSZ_CNT_HRSZ_SHIFT … #define ISPRSZ_CNT_HRSZ_MASK … #define ISPRSZ_CNT_VRSZ_SHIFT … #define ISPRSZ_CNT_VRSZ_MASK … #define ISPRSZ_CNT_HSTPH_SHIFT … #define ISPRSZ_CNT_HSTPH_MASK … #define ISPRSZ_CNT_VSTPH_SHIFT … #define ISPRSZ_CNT_VSTPH_MASK … #define ISPRSZ_CNT_YCPOS … #define ISPRSZ_CNT_INPTYP … #define ISPRSZ_CNT_INPSRC … #define ISPRSZ_CNT_CBILIN … #define ISPRSZ_OUT_SIZE_HORZ_SHIFT … #define ISPRSZ_OUT_SIZE_HORZ_MASK … #define ISPRSZ_OUT_SIZE_VERT_SHIFT … #define ISPRSZ_OUT_SIZE_VERT_MASK … #define ISPRSZ_IN_START_HORZ_ST_SHIFT … #define ISPRSZ_IN_START_HORZ_ST_MASK … #define ISPRSZ_IN_START_VERT_ST_SHIFT … #define ISPRSZ_IN_START_VERT_ST_MASK … #define ISPRSZ_IN_SIZE_HORZ_SHIFT … #define ISPRSZ_IN_SIZE_HORZ_MASK … #define ISPRSZ_IN_SIZE_VERT_SHIFT … #define ISPRSZ_IN_SIZE_VERT_MASK … #define ISPRSZ_SDR_INADD_ADDR_SHIFT … #define ISPRSZ_SDR_INADD_ADDR_MASK … #define ISPRSZ_SDR_INOFF_OFFSET_SHIFT … #define ISPRSZ_SDR_INOFF_OFFSET_MASK … #define ISPRSZ_SDR_OUTADD_ADDR_SHIFT … #define ISPRSZ_SDR_OUTADD_ADDR_MASK … #define ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT … #define ISPRSZ_SDR_OUTOFF_OFFSET_MASK … #define ISPRSZ_HFILT_COEF0_SHIFT … #define ISPRSZ_HFILT_COEF0_MASK … #define ISPRSZ_HFILT_COEF1_SHIFT … #define ISPRSZ_HFILT_COEF1_MASK … #define ISPRSZ_HFILT32_COEF2_SHIFT … #define ISPRSZ_HFILT32_COEF2_MASK … #define ISPRSZ_HFILT32_COEF3_SHIFT … #define ISPRSZ_HFILT32_COEF3_MASK … #define ISPRSZ_HFILT54_COEF4_SHIFT … #define ISPRSZ_HFILT54_COEF4_MASK … #define ISPRSZ_HFILT54_COEF5_SHIFT … #define ISPRSZ_HFILT54_COEF5_MASK … #define ISPRSZ_HFILT76_COEFF6_SHIFT … #define ISPRSZ_HFILT76_COEFF6_MASK … #define ISPRSZ_HFILT76_COEFF7_SHIFT … #define ISPRSZ_HFILT76_COEFF7_MASK … #define ISPRSZ_HFILT98_COEFF8_SHIFT … #define ISPRSZ_HFILT98_COEFF8_MASK … #define ISPRSZ_HFILT98_COEFF9_SHIFT … #define ISPRSZ_HFILT98_COEFF9_MASK … #define ISPRSZ_HFILT1110_COEF10_SHIFT … #define ISPRSZ_HFILT1110_COEF10_MASK … #define ISPRSZ_HFILT1110_COEF11_SHIFT … #define ISPRSZ_HFILT1110_COEF11_MASK … #define ISPRSZ_HFILT1312_COEFF12_SHIFT … #define ISPRSZ_HFILT1312_COEFF12_MASK … #define ISPRSZ_HFILT1312_COEFF13_SHIFT … #define ISPRSZ_HFILT1312_COEFF13_MASK … #define ISPRSZ_HFILT1514_COEFF14_SHIFT … #define ISPRSZ_HFILT1514_COEFF14_MASK … #define ISPRSZ_HFILT1514_COEFF15_SHIFT … #define ISPRSZ_HFILT1514_COEFF15_MASK … #define ISPRSZ_HFILT1716_COEF16_SHIFT … #define ISPRSZ_HFILT1716_COEF16_MASK … #define ISPRSZ_HFILT1716_COEF17_SHIFT … #define ISPRSZ_HFILT1716_COEF17_MASK … #define ISPRSZ_HFILT1918_COEF18_SHIFT … #define ISPRSZ_HFILT1918_COEF18_MASK … #define ISPRSZ_HFILT1918_COEF19_SHIFT … #define ISPRSZ_HFILT1918_COEF19_MASK … #define ISPRSZ_HFILT2120_COEF20_SHIFT … #define ISPRSZ_HFILT2120_COEF20_MASK … #define ISPRSZ_HFILT2120_COEF21_SHIFT … #define ISPRSZ_HFILT2120_COEF21_MASK … #define ISPRSZ_HFILT2322_COEF22_SHIFT … #define ISPRSZ_HFILT2322_COEF22_MASK … #define ISPRSZ_HFILT2322_COEF23_SHIFT … #define ISPRSZ_HFILT2322_COEF23_MASK … #define ISPRSZ_HFILT2524_COEF24_SHIFT … #define ISPRSZ_HFILT2524_COEF24_MASK … #define ISPRSZ_HFILT2524_COEF25_SHIFT … #define ISPRSZ_HFILT2524_COEF25_MASK … #define ISPRSZ_HFILT2726_COEF26_SHIFT … #define ISPRSZ_HFILT2726_COEF26_MASK … #define ISPRSZ_HFILT2726_COEF27_SHIFT … #define ISPRSZ_HFILT2726_COEF27_MASK … #define ISPRSZ_HFILT2928_COEF28_SHIFT … #define ISPRSZ_HFILT2928_COEF28_MASK … #define ISPRSZ_HFILT2928_COEF29_SHIFT … #define ISPRSZ_HFILT2928_COEF29_MASK … #define ISPRSZ_HFILT3130_COEF30_SHIFT … #define ISPRSZ_HFILT3130_COEF30_MASK … #define ISPRSZ_HFILT3130_COEF31_SHIFT … #define ISPRSZ_HFILT3130_COEF31_MASK … #define ISPRSZ_VFILT_COEF0_SHIFT … #define ISPRSZ_VFILT_COEF0_MASK … #define ISPRSZ_VFILT_COEF1_SHIFT … #define ISPRSZ_VFILT_COEF1_MASK … #define ISPRSZ_VFILT10_COEF0_SHIFT … #define ISPRSZ_VFILT10_COEF0_MASK … #define ISPRSZ_VFILT10_COEF1_SHIFT … #define ISPRSZ_VFILT10_COEF1_MASK … #define ISPRSZ_VFILT32_COEF2_SHIFT … #define ISPRSZ_VFILT32_COEF2_MASK … #define ISPRSZ_VFILT32_COEF3_SHIFT … #define ISPRSZ_VFILT32_COEF3_MASK … #define ISPRSZ_VFILT54_COEF4_SHIFT … #define ISPRSZ_VFILT54_COEF4_MASK … #define ISPRSZ_VFILT54_COEF5_SHIFT … #define ISPRSZ_VFILT54_COEF5_MASK … #define ISPRSZ_VFILT76_COEFF6_SHIFT … #define ISPRSZ_VFILT76_COEFF6_MASK … #define ISPRSZ_VFILT76_COEFF7_SHIFT … #define ISPRSZ_VFILT76_COEFF7_MASK … #define ISPRSZ_VFILT98_COEFF8_SHIFT … #define ISPRSZ_VFILT98_COEFF8_MASK … #define ISPRSZ_VFILT98_COEFF9_SHIFT … #define ISPRSZ_VFILT98_COEFF9_MASK … #define ISPRSZ_VFILT1110_COEF10_SHIFT … #define ISPRSZ_VFILT1110_COEF10_MASK … #define ISPRSZ_VFILT1110_COEF11_SHIFT … #define ISPRSZ_VFILT1110_COEF11_MASK … #define ISPRSZ_VFILT1312_COEFF12_SHIFT … #define ISPRSZ_VFILT1312_COEFF12_MASK … #define ISPRSZ_VFILT1312_COEFF13_SHIFT … #define ISPRSZ_VFILT1312_COEFF13_MASK … #define ISPRSZ_VFILT1514_COEFF14_SHIFT … #define ISPRSZ_VFILT1514_COEFF14_MASK … #define ISPRSZ_VFILT1514_COEFF15_SHIFT … #define ISPRSZ_VFILT1514_COEFF15_MASK … #define ISPRSZ_VFILT1716_COEF16_SHIFT … #define ISPRSZ_VFILT1716_COEF16_MASK … #define ISPRSZ_VFILT1716_COEF17_SHIFT … #define ISPRSZ_VFILT1716_COEF17_MASK … #define ISPRSZ_VFILT1918_COEF18_SHIFT … #define ISPRSZ_VFILT1918_COEF18_MASK … #define ISPRSZ_VFILT1918_COEF19_SHIFT … #define ISPRSZ_VFILT1918_COEF19_MASK … #define ISPRSZ_VFILT2120_COEF20_SHIFT … #define ISPRSZ_VFILT2120_COEF20_MASK … #define ISPRSZ_VFILT2120_COEF21_SHIFT … #define ISPRSZ_VFILT2120_COEF21_MASK … #define ISPRSZ_VFILT2322_COEF22_SHIFT … #define ISPRSZ_VFILT2322_COEF22_MASK … #define ISPRSZ_VFILT2322_COEF23_SHIFT … #define ISPRSZ_VFILT2322_COEF23_MASK … #define ISPRSZ_VFILT2524_COEF24_SHIFT … #define ISPRSZ_VFILT2524_COEF24_MASK … #define ISPRSZ_VFILT2524_COEF25_SHIFT … #define ISPRSZ_VFILT2524_COEF25_MASK … #define ISPRSZ_VFILT2726_COEF26_SHIFT … #define ISPRSZ_VFILT2726_COEF26_MASK … #define ISPRSZ_VFILT2726_COEF27_SHIFT … #define ISPRSZ_VFILT2726_COEF27_MASK … #define ISPRSZ_VFILT2928_COEF28_SHIFT … #define ISPRSZ_VFILT2928_COEF28_MASK … #define ISPRSZ_VFILT2928_COEF29_SHIFT … #define ISPRSZ_VFILT2928_COEF29_MASK … #define ISPRSZ_VFILT3130_COEF30_SHIFT … #define ISPRSZ_VFILT3130_COEF30_MASK … #define ISPRSZ_VFILT3130_COEF31_SHIFT … #define ISPRSZ_VFILT3130_COEF31_MASK … #define ISPRSZ_YENH_CORE_SHIFT … #define ISPRSZ_YENH_CORE_MASK … #define ISPRSZ_YENH_SLOP_SHIFT … #define ISPRSZ_YENH_SLOP_MASK … #define ISPRSZ_YENH_GAIN_SHIFT … #define ISPRSZ_YENH_GAIN_MASK … #define ISPRSZ_YENH_ALGO_SHIFT … #define ISPRSZ_YENH_ALGO_MASK … #define ISPH3A_PCR_AEW_ALAW_EN_SHIFT … #define ISPH3A_PCR_AF_MED_TH_SHIFT … #define ISPH3A_PCR_AF_RGBPOS_SHIFT … #define ISPH3A_PCR_AEW_AVE2LMT_SHIFT … #define ISPH3A_PCR_AEW_AVE2LMT_MASK … #define ISPH3A_PCR_BUSYAF … #define ISPH3A_PCR_BUSYAEAWB … #define ISPH3A_AEWWIN1_WINHC_SHIFT … #define ISPH3A_AEWWIN1_WINHC_MASK … #define ISPH3A_AEWWIN1_WINVC_SHIFT … #define ISPH3A_AEWWIN1_WINVC_MASK … #define ISPH3A_AEWWIN1_WINW_SHIFT … #define ISPH3A_AEWWIN1_WINW_MASK … #define ISPH3A_AEWWIN1_WINH_SHIFT … #define ISPH3A_AEWWIN1_WINH_MASK … #define ISPH3A_AEWINSTART_WINSH_SHIFT … #define ISPH3A_AEWINSTART_WINSH_MASK … #define ISPH3A_AEWINSTART_WINSV_SHIFT … #define ISPH3A_AEWINSTART_WINSV_MASK … #define ISPH3A_AEWINBLK_WINH_SHIFT … #define ISPH3A_AEWINBLK_WINH_MASK … #define ISPH3A_AEWINBLK_WINSV_SHIFT … #define ISPH3A_AEWINBLK_WINSV_MASK … #define ISPH3A_AEWSUBWIN_AEWINCH_SHIFT … #define ISPH3A_AEWSUBWIN_AEWINCH_MASK … #define ISPH3A_AEWSUBWIN_AEWINCV_SHIFT … #define ISPH3A_AEWSUBWIN_AEWINCV_MASK … #define ISPHIST_PCR_ENABLE_SHIFT … #define ISPHIST_PCR_ENABLE_MASK … #define ISPHIST_PCR_ENABLE … #define ISPHIST_PCR_BUSY … #define ISPHIST_CNT_DATASIZE_SHIFT … #define ISPHIST_CNT_DATASIZE_MASK … #define ISPHIST_CNT_CLEAR_SHIFT … #define ISPHIST_CNT_CLEAR_MASK … #define ISPHIST_CNT_CLEAR … #define ISPHIST_CNT_CFA_SHIFT … #define ISPHIST_CNT_CFA_MASK … #define ISPHIST_CNT_BINS_SHIFT … #define ISPHIST_CNT_BINS_MASK … #define ISPHIST_CNT_SOURCE_SHIFT … #define ISPHIST_CNT_SOURCE_MASK … #define ISPHIST_CNT_SHIFT_SHIFT … #define ISPHIST_CNT_SHIFT_MASK … #define ISPHIST_WB_GAIN_WG00_SHIFT … #define ISPHIST_WB_GAIN_WG00_MASK … #define ISPHIST_WB_GAIN_WG01_SHIFT … #define ISPHIST_WB_GAIN_WG01_MASK … #define ISPHIST_WB_GAIN_WG02_SHIFT … #define ISPHIST_WB_GAIN_WG02_MASK … #define ISPHIST_WB_GAIN_WG03_SHIFT … #define ISPHIST_WB_GAIN_WG03_MASK … #define ISPHIST_REG_START_END_MASK … #define ISPHIST_REG_START_SHIFT … #define ISPHIST_REG_END_SHIFT … #define ISPHIST_REG_START_MASK … #define ISPHIST_REG_END_MASK … #define ISPHIST_REG_MASK … #define ISPHIST_ADDR_SHIFT … #define ISPHIST_ADDR_MASK … #define ISPHIST_DATA_SHIFT … #define ISPHIST_DATA_MASK … #define ISPHIST_RADD_SHIFT … #define ISPHIST_RADD_MASK … #define ISPHIST_RADD_OFF_SHIFT … #define ISPHIST_RADD_OFF_MASK … #define ISPHIST_HV_INFO_HSIZE_SHIFT … #define ISPHIST_HV_INFO_HSIZE_MASK … #define ISPHIST_HV_INFO_VSIZE_SHIFT … #define ISPHIST_HV_INFO_VSIZE_MASK … #define ISPHIST_HV_INFO_MASK … #define ISPCCDC_LSC_ENABLE … #define ISPCCDC_LSC_BUSY … #define ISPCCDC_LSC_GAIN_MODE_N_MASK … #define ISPCCDC_LSC_GAIN_MODE_N_SHIFT … #define ISPCCDC_LSC_GAIN_MODE_M_MASK … #define ISPCCDC_LSC_GAIN_MODE_M_SHIFT … #define ISPCCDC_LSC_GAIN_FORMAT_MASK … #define ISPCCDC_LSC_GAIN_FORMAT_SHIFT … #define ISPCCDC_LSC_AFTER_REFORMATTER_MASK … #define ISPCCDC_LSC_INITIAL_X_MASK … #define ISPCCDC_LSC_INITIAL_X_SHIFT … #define ISPCCDC_LSC_INITIAL_Y_MASK … #define ISPCCDC_LSC_INITIAL_Y_SHIFT … /* ----------------------------------------------------------------------------- * CSI2 receiver registers (ES2.0) */ #define ISPCSI2_REVISION … #define ISPCSI2_SYSCONFIG … #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT … #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK … #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_FORCE … #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO … #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART … #define ISPCSI2_SYSCONFIG_SOFT_RESET … #define ISPCSI2_SYSCONFIG_AUTO_IDLE … #define ISPCSI2_SYSSTATUS … #define ISPCSI2_SYSSTATUS_RESET_DONE … #define ISPCSI2_IRQSTATUS … #define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ … #define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ … #define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ … #define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ … #define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ … #define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ … #define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ … #define ISPCSI2_IRQSTATUS_CONTEXT(n) … #define ISPCSI2_IRQENABLE … #define ISPCSI2_CTRL … #define ISPCSI2_CTRL_VP_CLK_EN … #define ISPCSI2_CTRL_VP_ONLY_EN … #define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT … #define ISPCSI2_CTRL_VP_OUT_CTRL_MASK … #define ISPCSI2_CTRL_DBG_EN … #define ISPCSI2_CTRL_BURST_SIZE_SHIFT … #define ISPCSI2_CTRL_BURST_SIZE_MASK … #define ISPCSI2_CTRL_FRAME … #define ISPCSI2_CTRL_ECC_EN … #define ISPCSI2_CTRL_SECURE … #define ISPCSI2_CTRL_IF_EN … #define ISPCSI2_DBG_H … #define ISPCSI2_GNQ … #define ISPCSI2_PHY_CFG … #define ISPCSI2_PHY_CFG_RESET_CTRL … #define ISPCSI2_PHY_CFG_RESET_DONE … #define ISPCSI2_PHY_CFG_PWR_CMD_SHIFT … #define ISPCSI2_PHY_CFG_PWR_CMD_MASK … #define ISPCSI2_PHY_CFG_PWR_CMD_OFF … #define ISPCSI2_PHY_CFG_PWR_CMD_ON … #define ISPCSI2_PHY_CFG_PWR_CMD_ULPW … #define ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT … #define ISPCSI2_PHY_CFG_PWR_STATUS_MASK … #define ISPCSI2_PHY_CFG_PWR_STATUS_OFF … #define ISPCSI2_PHY_CFG_PWR_STATUS_ON … #define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW … #define ISPCSI2_PHY_CFG_PWR_AUTO … #define ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n) … #define ISPCSI2_PHY_CFG_DATA_POL_MASK(n) … #define ISPCSI2_PHY_CFG_DATA_POL_PN(n) … #define ISPCSI2_PHY_CFG_DATA_POL_NP(n) … #define ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n) … #define ISPCSI2_PHY_CFG_DATA_POSITION_MASK(n) … #define ISPCSI2_PHY_CFG_DATA_POSITION_NC(n) … #define ISPCSI2_PHY_CFG_DATA_POSITION_1(n) … #define ISPCSI2_PHY_CFG_DATA_POSITION_2(n) … #define ISPCSI2_PHY_CFG_DATA_POSITION_3(n) … #define ISPCSI2_PHY_CFG_DATA_POSITION_4(n) … #define ISPCSI2_PHY_CFG_DATA_POSITION_5(n) … #define ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT … #define ISPCSI2_PHY_CFG_CLOCK_POL_MASK … #define ISPCSI2_PHY_CFG_CLOCK_POL_PN … #define ISPCSI2_PHY_CFG_CLOCK_POL_NP … #define ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT … #define ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK … #define ISPCSI2_PHY_CFG_CLOCK_POSITION_1 … #define ISPCSI2_PHY_CFG_CLOCK_POSITION_2 … #define ISPCSI2_PHY_CFG_CLOCK_POSITION_3 … #define ISPCSI2_PHY_CFG_CLOCK_POSITION_4 … #define ISPCSI2_PHY_CFG_CLOCK_POSITION_5 … #define ISPCSI2_PHY_IRQSTATUS … #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT … #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER … #define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 … #define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 … #define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 … #define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 … #define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 … #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 … #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 … #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 … #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 … #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 … #define ISPCSI2_PHY_IRQSTATUS_ERRESC5 … #define ISPCSI2_PHY_IRQSTATUS_ERRESC4 … #define ISPCSI2_PHY_IRQSTATUS_ERRESC3 … #define ISPCSI2_PHY_IRQSTATUS_ERRESC2 … #define ISPCSI2_PHY_IRQSTATUS_ERRESC1 … #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 … #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 … #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 … #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 … #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 … #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 … #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 … #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 … #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 … #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 … #define ISPCSI2_SHORT_PACKET … #define ISPCSI2_PHY_IRQENABLE … #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT … #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER … #define ISPCSI2_PHY_IRQENABLE_STATEULPM5 … #define ISPCSI2_PHY_IRQENABLE_STATEULPM4 … #define ISPCSI2_PHY_IRQENABLE_STATEULPM3 … #define ISPCSI2_PHY_IRQENABLE_STATEULPM2 … #define ISPCSI2_PHY_IRQENABLE_STATEULPM1 … #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 … #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 … #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 … #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 … #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 … #define ISPCSI2_PHY_IRQENABLE_ERRESC5 … #define ISPCSI2_PHY_IRQENABLE_ERRESC4 … #define ISPCSI2_PHY_IRQENABLE_ERRESC3 … #define ISPCSI2_PHY_IRQENABLE_ERRESC2 … #define ISPCSI2_PHY_IRQENABLE_ERRESC1 … #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 … #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 … #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 … #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 … #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 … #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 … #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 … #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 … #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 … #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 … #define ISPCSI2_DBG_P … #define ISPCSI2_TIMING … #define ISPCSI2_TIMING_FORCE_RX_MODE_IO(n) … #define ISPCSI2_TIMING_STOP_STATE_X16_IO(n) … #define ISPCSI2_TIMING_STOP_STATE_X4_IO(n) … #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n) … #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(n) … #define ISPCSI2_CTX_CTRL1(n) … #define ISPCSI2_CTX_CTRL1_COUNT_SHIFT … #define ISPCSI2_CTX_CTRL1_COUNT_MASK … #define ISPCSI2_CTX_CTRL1_EOF_EN … #define ISPCSI2_CTX_CTRL1_EOL_EN … #define ISPCSI2_CTX_CTRL1_CS_EN … #define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK … #define ISPCSI2_CTX_CTRL1_PING_PONG … #define ISPCSI2_CTX_CTRL1_CTX_EN … #define ISPCSI2_CTX_CTRL2(n) … #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT … #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK … #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT … #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK … #define ISPCSI2_CTX_CTRL2_DPCM_PRED … #define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT … #define ISPCSI2_CTX_CTRL2_FORMAT_MASK … #define ISPCSI2_CTX_CTRL2_FRAME_SHIFT … #define ISPCSI2_CTX_CTRL2_FRAME_MASK … #define ISPCSI2_CTX_DAT_OFST(n) … #define ISPCSI2_CTX_DAT_OFST_OFST_SHIFT … #define ISPCSI2_CTX_DAT_OFST_OFST_MASK … #define ISPCSI2_CTX_DAT_PING_ADDR(n) … #define ISPCSI2_CTX_DAT_PONG_ADDR(n) … #define ISPCSI2_CTX_IRQENABLE(n) … #define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ … #define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ … #define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ … #define ISPCSI2_CTX_IRQENABLE_CS_IRQ … #define ISPCSI2_CTX_IRQENABLE_LE_IRQ … #define ISPCSI2_CTX_IRQENABLE_LS_IRQ … #define ISPCSI2_CTX_IRQENABLE_FE_IRQ … #define ISPCSI2_CTX_IRQENABLE_FS_IRQ … #define ISPCSI2_CTX_IRQSTATUS(n) … #define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ … #define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ … #define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ … #define ISPCSI2_CTX_IRQSTATUS_CS_IRQ … #define ISPCSI2_CTX_IRQSTATUS_LE_IRQ … #define ISPCSI2_CTX_IRQSTATUS_LS_IRQ … #define ISPCSI2_CTX_IRQSTATUS_FE_IRQ … #define ISPCSI2_CTX_IRQSTATUS_FS_IRQ … #define ISPCSI2_CTX_CTRL3(n) … #define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT … #define ISPCSI2_CTX_CTRL3_ALPHA_MASK … /* This instance is for OMAP3630 only */ #define ISPCSI2_CTX_TRANSCODEH(n) … #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT … #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_MASK … #define ISPCSI2_CTX_TRANSCODEH_HSKIP_SHIFT … #define ISPCSI2_CTX_TRANSCODEH_HSKIP_MASK … #define ISPCSI2_CTX_TRANSCODEV(n) … #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT … #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_MASK … #define ISPCSI2_CTX_TRANSCODEV_VSKIP_SHIFT … #define ISPCSI2_CTX_TRANSCODEV_VSKIP_MASK … /* ----------------------------------------------------------------------------- * CSI PHY registers */ #define ISPCSIPHY_REG0 … #define ISPCSIPHY_REG0_THS_TERM_SHIFT … #define ISPCSIPHY_REG0_THS_TERM_MASK … #define ISPCSIPHY_REG0_THS_SETTLE_SHIFT … #define ISPCSIPHY_REG0_THS_SETTLE_MASK … #define ISPCSIPHY_REG1 … #define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK … /* This field is for OMAP3630 only */ #define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS … #define ISPCSIPHY_REG1_TCLK_TERM_SHIFT … #define ISPCSIPHY_REG1_TCLK_TERM_MASK … #define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_SHIFT … #define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_MASK … /* This field is for OMAP3430 only */ #define ISPCSIPHY_REG1_TCLK_MISS_SHIFT … #define ISPCSIPHY_REG1_TCLK_MISS_MASK … /* This field is for OMAP3630 only */ #define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT … #define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_MASK … #define ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT … #define ISPCSIPHY_REG1_TCLK_SETTLE_MASK … /* This register is for OMAP3630 only */ #define ISPCSIPHY_REG2 … #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT … #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK … #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT … #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK … #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT … #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK … #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT … #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK … #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT … #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_MASK … /* ----------------------------------------------------------------------------- * CONTROL registers for CSI-2 phy routing */ /* OMAP343X_CONTROL_CSIRXFE */ #define OMAP343X_CONTROL_CSIRXFE_CSIB_INV … #define OMAP343X_CONTROL_CSIRXFE_RESENABLE … #define OMAP343X_CONTROL_CSIRXFE_SELFORM … #define OMAP343X_CONTROL_CSIRXFE_PWRDNZ … #define OMAP343X_CONTROL_CSIRXFE_RESET … /* OMAP3630_CONTROL_CAMERA_PHY_CTRL */ #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT … #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT … #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY … #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE … #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK … #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_GPI … #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK … /* CCP2B: set to receive data from PHY2 instead of PHY1 */ #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 … #endif /* OMAP3_ISP_REG_H */
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