/* SPDX-License-Identifier: GPL-2.0 */ /* * Hantro VPU codec driver * * Copyright 2018 Google LLC. * Tomasz Figa <[email protected]> */ #ifndef HANTRO_G1_REGS_H_ #define HANTRO_G1_REGS_H_ #define G1_SWREG(nr) … /* Decoder registers. */ #define G1_REG_INTERRUPT … #define G1_REG_INTERRUPT_DEC_PIC_INF … #define G1_REG_INTERRUPT_DEC_TIMEOUT … #define G1_REG_INTERRUPT_DEC_SLICE_INT … #define G1_REG_INTERRUPT_DEC_ERROR_INT … #define G1_REG_INTERRUPT_DEC_ASO_INT … #define G1_REG_INTERRUPT_DEC_BUFFER_INT … #define G1_REG_INTERRUPT_DEC_BUS_INT … #define G1_REG_INTERRUPT_DEC_RDY_INT … #define G1_REG_INTERRUPT_DEC_IRQ … #define G1_REG_INTERRUPT_DEC_IRQ_DIS … #define G1_REG_INTERRUPT_DEC_E … #define G1_REG_CONFIG … #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) … #define G1_REG_CONFIG_DEC_TIMEOUT_E … #define G1_REG_CONFIG_DEC_STRSWAP32_E … #define G1_REG_CONFIG_DEC_STRENDIAN_E … #define G1_REG_CONFIG_DEC_INSWAP32_E … #define G1_REG_CONFIG_DEC_OUTSWAP32_E … #define G1_REG_CONFIG_DEC_DATA_DISC_E … #define G1_REG_CONFIG_TILED_MODE_MSB … #define G1_REG_CONFIG_DEC_OUT_TILED_E … #define G1_REG_CONFIG_DEC_LATENCY(x) … #define G1_REG_CONFIG_DEC_CLK_GATE_E … #define G1_REG_CONFIG_DEC_IN_ENDIAN … #define G1_REG_CONFIG_DEC_OUT_ENDIAN … #define G1_REG_CONFIG_PRIORITY_MODE(x) … #define G1_REG_CONFIG_TILED_MODE_LSB … #define G1_REG_CONFIG_DEC_ADV_PRE_DIS … #define G1_REG_CONFIG_DEC_SCMD_DIS … #define G1_REG_CONFIG_DEC_MAX_BURST(x) … #define G1_REG_DEC_CTRL0 … #define G1_REG_DEC_CTRL0_DEC_MODE(x) … #define G1_REG_DEC_CTRL0_RLC_MODE_E … #define G1_REG_DEC_CTRL0_SKIP_MODE … #define G1_REG_DEC_CTRL0_DIVX3_E … #define G1_REG_DEC_CTRL0_PJPEG_E … #define G1_REG_DEC_CTRL0_PIC_INTERLACE_E … #define G1_REG_DEC_CTRL0_PIC_FIELDMODE_E … #define G1_REG_DEC_CTRL0_PIC_B_E … #define G1_REG_DEC_CTRL0_PIC_INTER_E … #define G1_REG_DEC_CTRL0_PIC_TOPFIELD_E … #define G1_REG_DEC_CTRL0_FWD_INTERLACE_E … #define G1_REG_DEC_CTRL0_SORENSON_E … #define G1_REG_DEC_CTRL0_REF_TOPFIELD_E … #define G1_REG_DEC_CTRL0_DEC_OUT_DIS … #define G1_REG_DEC_CTRL0_FILTERING_DIS … #define G1_REG_DEC_CTRL0_WEBP_E … #define G1_REG_DEC_CTRL0_MVC_E … #define G1_REG_DEC_CTRL0_PIC_FIXED_QUANT … #define G1_REG_DEC_CTRL0_WRITE_MVS_E … #define G1_REG_DEC_CTRL0_REFTOPFIRST_E … #define G1_REG_DEC_CTRL0_SEQ_MBAFF_E … #define G1_REG_DEC_CTRL0_PICORD_COUNT_E … #define G1_REG_DEC_CTRL0_DEC_AHB_HLOCK_E … #define G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) … /* Setting AXI ID to 0xff to get auto generated ID to avoid possible conflicts */ #define G1_REG_DEC_CTRL0_DEC_AXI_AUTO … #define G1_REG_DEC_CTRL1 … #define G1_REG_DEC_CTRL1_PIC_MB_WIDTH(x) … #define G1_REG_DEC_CTRL1_MB_WIDTH_OFF(x) … #define G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x) … #define G1_REG_DEC_CTRL1_MB_HEIGHT_OFF(x) … #define G1_REG_DEC_CTRL1_ALT_SCAN_E … #define G1_REG_DEC_CTRL1_TOPFIELDFIRST_E … #define G1_REG_DEC_CTRL1_REF_FRAMES(x) … #define G1_REG_DEC_CTRL1_PIC_MB_W_EXT(x) … #define G1_REG_DEC_CTRL1_PIC_MB_H_EXT(x) … #define G1_REG_DEC_CTRL1_PIC_REFER_FLAG … #define G1_REG_DEC_CTRL2 … #define G1_REG_DEC_CTRL2_STRM_START_BIT(x) … #define G1_REG_DEC_CTRL2_SYNC_MARKER_E … #define G1_REG_DEC_CTRL2_TYPE1_QUANT_E … #define G1_REG_DEC_CTRL2_CH_QP_OFFSET(x) … #define G1_REG_DEC_CTRL2_CH_QP_OFFSET2(x) … #define G1_REG_DEC_CTRL2_FIELDPIC_FLAG_E … #define G1_REG_DEC_CTRL2_INTRADC_VLC_THR(x) … #define G1_REG_DEC_CTRL2_VOP_TIME_INCR(x) … #define G1_REG_DEC_CTRL2_DQ_PROFILE … #define G1_REG_DEC_CTRL2_DQBI_LEVEL … #define G1_REG_DEC_CTRL2_RANGE_RED_FRM_E … #define G1_REG_DEC_CTRL2_FAST_UVMC_E … #define G1_REG_DEC_CTRL2_TRANSDCTAB … #define G1_REG_DEC_CTRL2_TRANSACFRM(x) … #define G1_REG_DEC_CTRL2_TRANSACFRM2(x) … #define G1_REG_DEC_CTRL2_MB_MODE_TAB(x) … #define G1_REG_DEC_CTRL2_MVTAB(x) … #define G1_REG_DEC_CTRL2_CBPTAB(x) … #define G1_REG_DEC_CTRL2_2MV_BLK_PAT_TAB(x) … #define G1_REG_DEC_CTRL2_4MV_BLK_PAT_TAB(x) … #define G1_REG_DEC_CTRL2_QSCALE_TYPE … #define G1_REG_DEC_CTRL2_CON_MV_E … #define G1_REG_DEC_CTRL2_INTRA_DC_PREC(x) … #define G1_REG_DEC_CTRL2_INTRA_VLC_TAB … #define G1_REG_DEC_CTRL2_FRAME_PRED_DCT … #define G1_REG_DEC_CTRL2_JPEG_QTABLES(x) … #define G1_REG_DEC_CTRL2_JPEG_MODE(x) … #define G1_REG_DEC_CTRL2_JPEG_FILRIGHT_E … #define G1_REG_DEC_CTRL2_JPEG_STREAM_ALL … #define G1_REG_DEC_CTRL2_CR_AC_VLCTABLE … #define G1_REG_DEC_CTRL2_CB_AC_VLCTABLE … #define G1_REG_DEC_CTRL2_CR_DC_VLCTABLE … #define G1_REG_DEC_CTRL2_CB_DC_VLCTABLE … #define G1_REG_DEC_CTRL2_CR_DC_VLCTABLE3 … #define G1_REG_DEC_CTRL2_CB_DC_VLCTABLE3 … #define G1_REG_DEC_CTRL2_STRM1_START_BIT(x) … #define G1_REG_DEC_CTRL2_HUFFMAN_E … #define G1_REG_DEC_CTRL2_MULTISTREAM_E … #define G1_REG_DEC_CTRL2_BOOLEAN_VALUE(x) … #define G1_REG_DEC_CTRL2_BOOLEAN_RANGE(x) … #define G1_REG_DEC_CTRL2_ALPHA_OFFSET(x) … #define G1_REG_DEC_CTRL2_BETA_OFFSET(x) … #define G1_REG_DEC_CTRL3 … #define G1_REG_DEC_CTRL3_START_CODE_E … #define G1_REG_DEC_CTRL3_INIT_QP(x) … #define G1_REG_DEC_CTRL3_CH_8PIX_ILEAV_E … #define G1_REG_DEC_CTRL3_STREAM_LEN_EXT(x) … #define G1_REG_DEC_CTRL3_STREAM_LEN(x) … #define G1_REG_DEC_CTRL4 … #define G1_REG_DEC_CTRL4_CABAC_E … #define G1_REG_DEC_CTRL4_BLACKWHITE_E … #define G1_REG_DEC_CTRL4_DIR_8X8_INFER_E … #define G1_REG_DEC_CTRL4_WEIGHT_PRED_E … #define G1_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(x) … #define G1_REG_DEC_CTRL4_AVS_H264_H_EXT … #define G1_REG_DEC_CTRL4_FRAMENUM_LEN(x) … #define G1_REG_DEC_CTRL4_FRAMENUM(x) … #define G1_REG_DEC_CTRL4_BITPLANE0_E … #define G1_REG_DEC_CTRL4_BITPLANE1_E … #define G1_REG_DEC_CTRL4_BITPLANE2_E … #define G1_REG_DEC_CTRL4_ALT_PQUANT(x) … #define G1_REG_DEC_CTRL4_DQ_EDGES(x) … #define G1_REG_DEC_CTRL4_TTMBF … #define G1_REG_DEC_CTRL4_PQINDEX(x) … #define G1_REG_DEC_CTRL4_VC1_HEIGHT_EXT … #define G1_REG_DEC_CTRL4_BILIN_MC_E … #define G1_REG_DEC_CTRL4_UNIQP_E … #define G1_REG_DEC_CTRL4_HALFQP_E … #define G1_REG_DEC_CTRL4_TTFRM(x) … #define G1_REG_DEC_CTRL4_2ND_BYTE_EMUL_E … #define G1_REG_DEC_CTRL4_DQUANT_E … #define G1_REG_DEC_CTRL4_VC1_ADV_E … #define G1_REG_DEC_CTRL4_PJPEG_FILDOWN_E … #define G1_REG_DEC_CTRL4_PJPEG_WDIV8 … #define G1_REG_DEC_CTRL4_PJPEG_HDIV8 … #define G1_REG_DEC_CTRL4_PJPEG_AH(x) … #define G1_REG_DEC_CTRL4_PJPEG_AL(x) … #define G1_REG_DEC_CTRL4_PJPEG_SS(x) … #define G1_REG_DEC_CTRL4_PJPEG_SE(x) … #define G1_REG_DEC_CTRL4_DCT1_START_BIT(x) … #define G1_REG_DEC_CTRL4_DCT2_START_BIT(x) … #define G1_REG_DEC_CTRL4_CH_MV_RES … #define G1_REG_DEC_CTRL4_INIT_DC_MATCH0(x) … #define G1_REG_DEC_CTRL4_INIT_DC_MATCH1(x) … #define G1_REG_DEC_CTRL4_VP7_VERSION … #define G1_REG_DEC_CTRL5 … #define G1_REG_DEC_CTRL5_CONST_INTRA_E … #define G1_REG_DEC_CTRL5_FILT_CTRL_PRES … #define G1_REG_DEC_CTRL5_RDPIC_CNT_PRES … #define G1_REG_DEC_CTRL5_8X8TRANS_FLAG_E … #define G1_REG_DEC_CTRL5_REFPIC_MK_LEN(x) … #define G1_REG_DEC_CTRL5_IDR_PIC_E … #define G1_REG_DEC_CTRL5_IDR_PIC_ID(x) … #define G1_REG_DEC_CTRL5_MV_SCALEFACTOR(x) … #define G1_REG_DEC_CTRL5_REF_DIST_FWD(x) … #define G1_REG_DEC_CTRL5_REF_DIST_BWD(x) … #define G1_REG_DEC_CTRL5_LOOP_FILT_LIMIT(x) … #define G1_REG_DEC_CTRL5_VARIANCE_TEST_E … #define G1_REG_DEC_CTRL5_MV_THRESHOLD(x) … #define G1_REG_DEC_CTRL5_VAR_THRESHOLD(x) … #define G1_REG_DEC_CTRL5_DIVX_IDCT_E … #define G1_REG_DEC_CTRL5_DIVX3_SLICE_SIZE(x) … #define G1_REG_DEC_CTRL5_PJPEG_REST_FREQ(x) … #define G1_REG_DEC_CTRL5_RV_PROFILE(x) … #define G1_REG_DEC_CTRL5_RV_OSV_QUANT(x) … #define G1_REG_DEC_CTRL5_RV_FWD_SCALE(x) … #define G1_REG_DEC_CTRL5_RV_BWD_SCALE(x) … #define G1_REG_DEC_CTRL5_INIT_DC_COMP0(x) … #define G1_REG_DEC_CTRL5_INIT_DC_COMP1(x) … #define G1_REG_DEC_CTRL6 … #define G1_REG_DEC_CTRL6_PPS_ID(x) … #define G1_REG_DEC_CTRL6_REFIDX1_ACTIVE(x) … #define G1_REG_DEC_CTRL6_REFIDX0_ACTIVE(x) … #define G1_REG_DEC_CTRL6_POC_LENGTH(x) … #define G1_REG_DEC_CTRL6_ICOMP0_E … #define G1_REG_DEC_CTRL6_ISCALE0(x) … #define G1_REG_DEC_CTRL6_ISHIFT0(x) … #define G1_REG_DEC_CTRL6_STREAM1_LEN(x) … #define G1_REG_DEC_CTRL6_PIC_SLICE_AM(x) … #define G1_REG_DEC_CTRL6_COEFFS_PART_AM(x) … #define G1_REG_FWD_PIC(i) … #define G1_REG_FWD_PIC_PINIT_RLIST_F5(x) … #define G1_REG_FWD_PIC_PINIT_RLIST_F4(x) … #define G1_REG_FWD_PIC_PINIT_RLIST_F3(x) … #define G1_REG_FWD_PIC_PINIT_RLIST_F2(x) … #define G1_REG_FWD_PIC_PINIT_RLIST_F1(x) … #define G1_REG_FWD_PIC_PINIT_RLIST_F0(x) … #define G1_REG_FWD_PIC1_ICOMP1_E … #define G1_REG_FWD_PIC1_ISCALE1(x) … #define G1_REG_FWD_PIC1_ISHIFT1(x) … #define G1_REG_FWD_PIC1_SEGMENT_BASE(x) … #define G1_REG_FWD_PIC1_SEGMENT_UPD_E … #define G1_REG_FWD_PIC1_SEGMENT_E … #define G1_REG_DEC_CTRL7 … #define G1_REG_DEC_CTRL7_PINIT_RLIST_F15(x) … #define G1_REG_DEC_CTRL7_PINIT_RLIST_F14(x) … #define G1_REG_DEC_CTRL7_PINIT_RLIST_F13(x) … #define G1_REG_DEC_CTRL7_PINIT_RLIST_F12(x) … #define G1_REG_DEC_CTRL7_PINIT_RLIST_F11(x) … #define G1_REG_DEC_CTRL7_PINIT_RLIST_F10(x) … #define G1_REG_DEC_CTRL7_ICOMP2_E … #define G1_REG_DEC_CTRL7_ISCALE2(x) … #define G1_REG_DEC_CTRL7_ISHIFT2(x) … #define G1_REG_DEC_CTRL7_DCT3_START_BIT(x) … #define G1_REG_DEC_CTRL7_DCT4_START_BIT(x) … #define G1_REG_DEC_CTRL7_DCT5_START_BIT(x) … #define G1_REG_DEC_CTRL7_DCT6_START_BIT(x) … #define G1_REG_DEC_CTRL7_DCT7_START_BIT(x) … #define G1_REG_ADDR_STR … #define G1_REG_ADDR_DST … #define G1_REG_ADDR_REF(i) … #define G1_REG_ADDR_REF_FIELD_E … #define G1_REG_ADDR_REF_TOPC_E … #define G1_REG_REF_PIC(i) … #define G1_REG_REF_PIC_FILT_TYPE_E … #define G1_REG_REF_PIC_FILT_SHARPNESS(x) … #define G1_REG_REF_PIC_MB_ADJ_0(x) … #define G1_REG_REF_PIC_MB_ADJ_1(x) … #define G1_REG_REF_PIC_MB_ADJ_2(x) … #define G1_REG_REF_PIC_MB_ADJ_3(x) … #define G1_REG_REF_PIC_REFER1_NBR(x) … #define G1_REG_REF_PIC_REFER0_NBR(x) … #define G1_REG_REF_PIC_LF_LEVEL_0(x) … #define G1_REG_REF_PIC_LF_LEVEL_1(x) … #define G1_REG_REF_PIC_LF_LEVEL_2(x) … #define G1_REG_REF_PIC_LF_LEVEL_3(x) … #define G1_REG_REF_PIC_QUANT_DELTA_0(x) … #define G1_REG_REF_PIC_QUANT_DELTA_1(x) … #define G1_REG_REF_PIC_QUANT_0(x) … #define G1_REG_REF_PIC_QUANT_1(x) … #define G1_REG_LT_REF … #define G1_REG_VALID_REF … #define G1_REG_ADDR_QTABLE … #define G1_REG_ADDR_DIR_MV … #define G1_REG_BD_REF_PIC(i) … #define G1_REG_BD_REF_PIC_BINIT_RLIST_B2(x) … #define G1_REG_BD_REF_PIC_BINIT_RLIST_F2(x) … #define G1_REG_BD_REF_PIC_BINIT_RLIST_B1(x) … #define G1_REG_BD_REF_PIC_BINIT_RLIST_F1(x) … #define G1_REG_BD_REF_PIC_BINIT_RLIST_B0(x) … #define G1_REG_BD_REF_PIC_BINIT_RLIST_F0(x) … #define G1_REG_BD_REF_PIC_PRED_TAP_2_M1(x) … #define G1_REG_BD_REF_PIC_PRED_TAP_2_4(x) … #define G1_REG_BD_REF_PIC_PRED_TAP_4_M1(x) … #define G1_REG_BD_REF_PIC_PRED_TAP_4_4(x) … #define G1_REG_BD_REF_PIC_PRED_TAP_6_M1(x) … #define G1_REG_BD_REF_PIC_PRED_TAP_6_4(x) … #define G1_REG_BD_REF_PIC_QUANT_DELTA_2(x) … #define G1_REG_BD_REF_PIC_QUANT_DELTA_3(x) … #define G1_REG_BD_REF_PIC_QUANT_2(x) … #define G1_REG_BD_REF_PIC_QUANT_3(x) … #define G1_REG_BD_P_REF_PIC … #define G1_REG_BD_P_REF_PIC_QUANT_DELTA_4(x) … #define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x) … #define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2(x) … #define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F1(x) … #define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0(x) … #define G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15(x) … #define G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(x) … #define G1_REG_ERR_CONC … #define G1_REG_ERR_CONC_STARTMB_X(x) … #define G1_REG_ERR_CONC_STARTMB_Y(x) … #define G1_REG_PRED_FLT … #define G1_REG_PRED_FLT_PRED_BC_TAP_0_0(x) … #define G1_REG_PRED_FLT_PRED_BC_TAP_0_1(x) … #define G1_REG_PRED_FLT_PRED_BC_TAP_0_2(x) … #define G1_REG_REF_BUF_CTRL … #define G1_REG_REF_BUF_CTRL_REFBU_E … #define G1_REG_REF_BUF_CTRL_REFBU_THR(x) … #define G1_REG_REF_BUF_CTRL_REFBU_PICID(x) … #define G1_REG_REF_BUF_CTRL_REFBU_EVAL_E … #define G1_REG_REF_BUF_CTRL_REFBU_FPARMOD_E … #define G1_REG_REF_BUF_CTRL_REFBU_Y_OFFSET(x) … #define G1_REG_REF_BUF_CTRL2 … #define G1_REG_REF_BUF_CTRL2_REFBU2_BUF_E … #define G1_REG_REF_BUF_CTRL2_REFBU2_THR(x) … #define G1_REG_REF_BUF_CTRL2_REFBU2_PICID(x) … #define G1_REG_REF_BUF_CTRL2_APF_THRESHOLD(x) … #define G1_REG_SOFT_RESET … /* Post-processor registers. */ #define G1_REG_PP_INTERRUPT … #define G1_REG_PP_READY_IRQ … #define G1_REG_PP_IRQ … #define G1_REG_PP_IRQ_DIS … #define G1_REG_PP_PIPELINE_EN … #define G1_REG_PP_EXTERNAL_TRIGGER … #define G1_REG_PP_DEV_CONFIG … #define G1_REG_PP_AXI_RD_ID(v) … #define G1_REG_PP_AXI_WR_ID(v) … #define G1_REG_PP_INSWAP32_E(v) … #define G1_REG_PP_DATA_DISC_E(v) … #define G1_REG_PP_CLK_GATE_E(v) … #define G1_REG_PP_IN_ENDIAN(v) … #define G1_REG_PP_OUT_ENDIAN(v) … #define G1_REG_PP_OUTSWAP32_E(v) … #define G1_REG_PP_MAX_BURST(v) … #define G1_REG_PP_IN_LUMA_BASE … #define G1_REG_PP_IN_CB_BASE … #define G1_REG_PP_IN_CR_BASE … #define G1_REG_PP_OUT_LUMA_BASE … #define G1_REG_PP_OUT_CHROMA_BASE … #define G1_REG_PP_CONTRAST_ADJUST … #define G1_REG_PP_COLOR_CONVERSION … #define G1_REG_PP_COLOR_CONVERSION0 … #define G1_REG_PP_COLOR_CONVERSION1 … #define G1_REG_PP_INPUT_SIZE … #define G1_REG_PP_INPUT_SIZE_HEIGHT(v) … #define G1_REG_PP_INPUT_SIZE_WIDTH(v) … #define G1_REG_PP_SCALING0 … #define G1_REG_PP_PADD_R(v) … #define G1_REG_PP_PADD_G(v) … #define G1_REG_PP_RANGEMAP_Y(v) … #define G1_REG_PP_RANGEMAP_C(v) … #define G1_REG_PP_YCBCR_RANGE(v) … #define G1_REG_PP_RGB_16(v) … #define G1_REG_PP_SCALING1 … #define G1_REG_PP_PADD_B(v) … #define G1_REG_PP_MASK_R … #define G1_REG_PP_MASK_G … #define G1_REG_PP_MASK_B … #define G1_REG_PP_CONTROL … #define G1_REG_PP_CONTROL_IN_FMT(v) … #define G1_REG_PP_CONTROL_OUT_FMT(v) … #define G1_REG_PP_CONTROL_OUT_HEIGHT(v) … #define G1_REG_PP_CONTROL_OUT_WIDTH(v) … #define G1_REG_PP_MASK1_ORIG_WIDTH … #define G1_REG_PP_ORIG_WIDTH(v) … #define G1_REG_PP_DISPLAY_WIDTH … #define G1_REG_PP_FUSE … #endif /* HANTRO_G1_REGS_H_ */
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