// SPDX-License-Identifier: GPL-2.0 /* * Rockchip VPU codec vp8 decode driver * * Copyright (C) 2014 Rockchip Electronics Co., Ltd. * ZhiChao Yu <[email protected]> * * Copyright (C) 2014 Google LLC. * Tomasz Figa <[email protected]> * * Copyright (C) 2015 Rockchip Electronics Co., Ltd. * Alpha Lin <[email protected]> */ #include <media/v4l2-mem2mem.h> #include "hantro_hw.h" #include "hantro.h" #include "hantro_g1_regs.h" #define VDPU_REG_DEC_CTRL0 … #define VDPU_REG_STREAM_LEN … #define VDPU_REG_DEC_FORMAT … #define VDPU_REG_DEC_CTRL0_DEC_MODE(x) … #define VDPU_REG_DATA_ENDIAN … #define VDPU_REG_CONFIG_DEC_STRENDIAN_E … #define VDPU_REG_CONFIG_DEC_STRSWAP32_E … #define VDPU_REG_CONFIG_DEC_OUTSWAP32_E … #define VDPU_REG_CONFIG_DEC_INSWAP32_E … #define VDPU_REG_CONFIG_DEC_OUT_ENDIAN … #define VDPU_REG_CONFIG_DEC_IN_ENDIAN … #define VDPU_REG_AXI_CTRL … #define VDPU_REG_CONFIG_DEC_MAX_BURST(x) … #define VDPU_REG_EN_FLAGS … #define VDPU_REG_DEC_CTRL0_PIC_INTER_E … #define VDPU_REG_CONFIG_DEC_TIMEOUT_E … #define VDPU_REG_CONFIG_DEC_CLK_GATE_E … #define VDPU_REG_PRED_FLT … #define VDPU_REG_ADDR_QTABLE … #define VDPU_REG_ADDR_DST … #define VDPU_REG_ADDR_STR … #define VDPU_REG_VP8_PIC_MB_SIZE … #define VDPU_REG_VP8_DCT_START_BIT … #define VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT … #define VDPU_REG_DEC_CTRL4_BILIN_MC_E … #define VDPU_REG_VP8_CTRL0 … #define VDPU_REG_VP8_DATA_VAL … #define VDPU_REG_PRED_FLT7 … #define VDPU_REG_PRED_FLT8 … #define VDPU_REG_PRED_FLT9 … #define VDPU_REG_PRED_FLT10 … #define VDPU_REG_FILTER_LEVEL … #define VDPU_REG_VP8_QUANTER0 … #define VDPU_REG_VP8_ADDR_REF0 … #define VDPU_REG_FILTER_MB_ADJ … #define VDPU_REG_REF_PIC_FILT_TYPE_E … #define VDPU_REG_REF_PIC_FILT_SHARPNESS(x) … #define VDPU_REG_FILTER_REF_ADJ … #define VDPU_REG_VP8_ADDR_REF2_5(i) … #define VDPU_REG_VP8_GREF_SIGN_BIAS … #define VDPU_REG_VP8_AREF_SIGN_BIAS … #define VDPU_REG_VP8_DCT_BASE(i) … #define VDPU_REG_VP8_ADDR_CTRL_PART … #define VDPU_REG_VP8_SEGMENT_VAL … #define VDPU_REG_FWD_PIC1_SEGMENT_BASE(x) … #define VDPU_REG_FWD_PIC1_SEGMENT_UPD_E … #define VDPU_REG_FWD_PIC1_SEGMENT_E … #define VDPU_REG_VP8_DCT_START_BIT2 … #define VDPU_REG_VP8_QUANTER1 … #define VDPU_REG_VP8_QUANTER2 … #define VDPU_REG_PRED_FLT1 … #define VDPU_REG_PRED_FLT2 … #define VDPU_REG_PRED_FLT3 … #define VDPU_REG_PRED_FLT4 … #define VDPU_REG_PRED_FLT5 … #define VDPU_REG_PRED_FLT6 … static const struct hantro_reg vp8_dec_dct_base[8] = …; static const struct hantro_reg vp8_dec_lf_level[4] = …; static const struct hantro_reg vp8_dec_mb_adj[4] = …; static const struct hantro_reg vp8_dec_ref_adj[4] = …; static const struct hantro_reg vp8_dec_quant[4] = …; static const struct hantro_reg vp8_dec_quant_delta[5] = …; static const struct hantro_reg vp8_dec_dct_start_bits[8] = …; static const struct hantro_reg vp8_dec_pred_bc_tap[8][6] = …; static const struct hantro_reg vp8_dec_mb_start_bit = …; static const struct hantro_reg vp8_dec_mb_aligned_data_len = …; static const struct hantro_reg vp8_dec_num_dct_partitions = …; static const struct hantro_reg vp8_dec_stream_len = …; static const struct hantro_reg vp8_dec_mb_width = …; static const struct hantro_reg vp8_dec_mb_height = …; static const struct hantro_reg vp8_dec_mb_width_ext = …; static const struct hantro_reg vp8_dec_mb_height_ext = …; static const struct hantro_reg vp8_dec_bool_range = …; static const struct hantro_reg vp8_dec_bool_value = …; static const struct hantro_reg vp8_dec_filter_disable = …; static const struct hantro_reg vp8_dec_skip_mode = …; static const struct hantro_reg vp8_dec_start_dec = …; static void cfg_lf(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp8_frame *hdr) { … } static void cfg_qp(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp8_frame *hdr) { … } static void cfg_parts(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp8_frame *hdr) { … } /* * prediction filter taps * normal 6-tap filters */ static void cfg_tap(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp8_frame *hdr) { … } static void cfg_ref(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp8_frame *hdr, struct vb2_v4l2_buffer *vb2_dst) { … } static void cfg_buffers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp8_frame *hdr, struct vb2_v4l2_buffer *vb2_dst) { … } int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx) { … }
Codebase Browser
linux