linux/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2023, Collabora
 *
 * Author: Benjamin Gaignard <[email protected]>
 */

#include <media/v4l2-mem2mem.h>
#include "hantro.h"
#include "hantro_v4l2.h"
#include "rockchip_vpu981_regs.h"

#define AV1_DEC_MODE
#define GM_GLOBAL_MODELS_PER_FRAME
#define GLOBAL_MODEL_TOTAL_SIZE
#define GLOBAL_MODEL_SIZE
#define AV1_MAX_TILES
#define AV1_TILE_INFO_SIZE
#define AV1DEC_MAX_PIC_BUFFERS
#define AV1_REF_SCALE_SHIFT
#define AV1_INVALID_IDX
#define MAX_FRAME_DISTANCE
#define AV1_PRIMARY_REF_NONE
#define AV1_TILE_SIZE
/*
 * These 3 values aren't defined enum v4l2_av1_segment_feature because
 * they are not part of the specification
 */
#define V4L2_AV1_SEG_LVL_ALT_LF_Y_H
#define V4L2_AV1_SEG_LVL_ALT_LF_U
#define V4L2_AV1_SEG_LVL_ALT_LF_V

#define SUPERRES_SCALE_BITS
#define SCALE_NUMERATOR
#define SUPERRES_SCALE_DENOMINATOR_MIN

#define RS_SUBPEL_BITS
#define RS_SUBPEL_MASK
#define RS_SCALE_SUBPEL_BITS
#define RS_SCALE_SUBPEL_MASK
#define RS_SCALE_EXTRA_BITS
#define RS_SCALE_EXTRA_OFF

#define IS_INTRA(type)

#define LST_BUF_IDX
#define LST2_BUF_IDX
#define LST3_BUF_IDX
#define GLD_BUF_IDX
#define BWD_BUF_IDX
#define ALT2_BUF_IDX
#define ALT_BUF_IDX

#define DIV_LUT_PREC_BITS
#define DIV_LUT_BITS
#define DIV_LUT_NUM
#define WARP_PARAM_REDUCE_BITS
#define WARPEDMODEL_PREC_BITS

#define AV1_DIV_ROUND_UP_POW2(value, n)

#define AV1_DIV_ROUND_UP_POW2_SIGNED(value, n)

struct rockchip_av1_film_grain {};

static const short div_lut[DIV_LUT_NUM + 1] =;

static int rockchip_vpu981_get_frame_index(struct hantro_ctx *ctx, int ref)
{}

static int rockchip_vpu981_get_order_hint(struct hantro_ctx *ctx, int ref)
{}

static int rockchip_vpu981_av1_dec_frame_ref(struct hantro_ctx *ctx,
					     u64 timestamp)
{}

static void rockchip_vpu981_av1_dec_frame_unref(struct hantro_ctx *ctx, int idx)
{}

static void rockchip_vpu981_av1_dec_clean_refs(struct hantro_ctx *ctx)
{}

static size_t rockchip_vpu981_av1_dec_luma_size(struct hantro_ctx *ctx)
{}

static size_t rockchip_vpu981_av1_dec_chroma_size(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_av1_dec_tiles_free(struct hantro_ctx *ctx)
{}

static int rockchip_vpu981_av1_dec_tiles_reallocate(struct hantro_ctx *ctx)
{}

void rockchip_vpu981_av1_dec_exit(struct hantro_ctx *ctx)
{}

int rockchip_vpu981_av1_dec_init(struct hantro_ctx *ctx)
{}

static int rockchip_vpu981_av1_dec_prepare_run(struct hantro_ctx *ctx)
{}

static inline int rockchip_vpu981_av1_dec_get_msb(u32 n)
{}

static short rockchip_vpu981_av1_dec_resolve_divisor_32(u32 d, short *shift)
{}

static void
rockchip_vpu981_av1_dec_get_shear_params(const u32 *params, s64 *alpha,
					 s64 *beta, s64 *gamma, s64 *delta)
{}

static void rockchip_vpu981_av1_dec_set_global_model(struct hantro_ctx *ctx)
{}

static int rockchip_vpu981_av1_tile_log2(int target)
{}

static void rockchip_vpu981_av1_dec_set_tile_info(struct hantro_ctx *ctx)
{}

static int rockchip_vpu981_av1_dec_get_dist(struct hantro_ctx *ctx,
					    int a, int b)
{}

static void rockchip_vpu981_av1_dec_set_frame_sign_bias(struct hantro_ctx *ctx)
{}

static bool
rockchip_vpu981_av1_dec_set_ref(struct hantro_ctx *ctx, int ref, int idx,
				int width, int height)
{}

static void rockchip_vpu981_av1_dec_set_sign_bias(struct hantro_ctx *ctx,
						  int ref, int val)
{}

static void rockchip_vpu981_av1_dec_set_segmentation(struct hantro_ctx *ctx)
{}

static bool rockchip_vpu981_av1_dec_is_lossless(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_av1_dec_set_loopfilter(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_av1_dec_update_prob(struct hantro_ctx *ctx)
{}

void rockchip_vpu981_av1_dec_done(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_av1_dec_set_prob(struct hantro_ctx *ctx)
{}

static void
rockchip_vpu981_av1_dec_init_scaling_function(const u8 *values, const u8 *scaling,
					      u8 num_points, u8 *scaling_lut)
{}

static void rockchip_vpu981_av1_dec_set_fgs(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_av1_dec_set_cdef(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_av1_dec_set_lr(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_av1_dec_set_superres_params(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_av1_dec_set_picture_dimensions(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_av1_dec_set_other_frames(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_av1_dec_set_reference_frames(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx)
{}

static void
rockchip_vpu981_av1_dec_set_input_buffer(struct hantro_ctx *ctx,
					 struct vb2_v4l2_buffer *vb2_src)
{}

static void
rockchip_vpu981_av1_dec_set_output_buffer(struct hantro_ctx *ctx)
{}

int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_postproc_enable(struct hantro_ctx *ctx)
{}

static void rockchip_vpu981_postproc_disable(struct hantro_ctx *ctx)
{}

const struct hantro_postproc_ops rockchip_vpu981_postproc_ops =;