// SPDX-License-Identifier: GPL-2.0 /* * Xilinx Video IP Core * * Copyright (C) 2013-2015 Ideas on Board * Copyright (C) 2013-2015 Xilinx, Inc. * * Contacts: Hyun Kwon <[email protected]> * Laurent Pinchart <[email protected]> */ #ifndef __DT_BINDINGS_MEDIA_XILINX_VIP_H__ #define __DT_BINDINGS_MEDIA_XILINX_VIP_H__ /* * Video format codes as defined in "AXI4-Stream Video IP and System Design * Guide". */ #define XVIP_VF_YUV_422 … #define XVIP_VF_YUV_444 … #define XVIP_VF_RBG … #define XVIP_VF_YUV_420 … #define XVIP_VF_YUVA_422 … #define XVIP_VF_YUVA_444 … #define XVIP_VF_RGBA … #define XVIP_VF_YUVA_420 … #define XVIP_VF_YUVD_422 … #define XVIP_VF_YUVD_444 … #define XVIP_VF_RGBD … #define XVIP_VF_YUVD_420 … #define XVIP_VF_MONO_SENSOR … #define XVIP_VF_CUSTOM2 … #define XVIP_VF_CUSTOM3 … #define XVIP_VF_CUSTOM4 … #endif /* __DT_BINDINGS_MEDIA_XILINX_VIP_H__ */
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