/* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Video IP Core * * Copyright (C) 2013-2015 Ideas on Board * Copyright (C) 2013-2015 Xilinx, Inc. * * Contacts: Hyun Kwon <[email protected]> * Laurent Pinchart <[email protected]> */ #ifndef __XILINX_VIP_H__ #define __XILINX_VIP_H__ #include <linux/bitops.h> #include <linux/io.h> #include <media/v4l2-subdev.h> struct clk; /* * Minimum and maximum width and height common to most video IP cores. IP * cores with different requirements must define their own values. */ #define XVIP_MIN_WIDTH … #define XVIP_MAX_WIDTH … #define XVIP_MIN_HEIGHT … #define XVIP_MAX_HEIGHT … /* * Pad IDs. IP cores with multiple inputs or outputs should define their own * values. */ #define XVIP_PAD_SINK … #define XVIP_PAD_SOURCE … /* Xilinx Video IP Control Registers */ #define XVIP_CTRL_CONTROL … #define XVIP_CTRL_CONTROL_SW_ENABLE … #define XVIP_CTRL_CONTROL_REG_UPDATE … #define XVIP_CTRL_CONTROL_BYPASS … #define XVIP_CTRL_CONTROL_TEST_PATTERN … #define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET … #define XVIP_CTRL_CONTROL_SW_RESET … #define XVIP_CTRL_STATUS … #define XVIP_CTRL_STATUS_PROC_STARTED … #define XVIP_CTRL_STATUS_EOF … #define XVIP_CTRL_ERROR … #define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY … #define XVIP_CTRL_ERROR_SLAVE_EOL_LATE … #define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY … #define XVIP_CTRL_ERROR_SLAVE_SOF_LATE … #define XVIP_CTRL_IRQ_ENABLE … #define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED … #define XVIP_CTRL_IRQ_EOF … #define XVIP_CTRL_VERSION … #define XVIP_CTRL_VERSION_MAJOR_MASK … #define XVIP_CTRL_VERSION_MAJOR_SHIFT … #define XVIP_CTRL_VERSION_MINOR_MASK … #define XVIP_CTRL_VERSION_MINOR_SHIFT … #define XVIP_CTRL_VERSION_REVISION_MASK … #define XVIP_CTRL_VERSION_REVISION_SHIFT … #define XVIP_CTRL_VERSION_PATCH_MASK … #define XVIP_CTRL_VERSION_PATCH_SHIFT … #define XVIP_CTRL_VERSION_INTERNAL_MASK … #define XVIP_CTRL_VERSION_INTERNAL_SHIFT … /* Xilinx Video IP Timing Registers */ #define XVIP_ACTIVE_SIZE … #define XVIP_ACTIVE_VSIZE_MASK … #define XVIP_ACTIVE_VSIZE_SHIFT … #define XVIP_ACTIVE_HSIZE_MASK … #define XVIP_ACTIVE_HSIZE_SHIFT … #define XVIP_ENCODING … #define XVIP_ENCODING_NBITS_8 … #define XVIP_ENCODING_NBITS_10 … #define XVIP_ENCODING_NBITS_12 … #define XVIP_ENCODING_NBITS_16 … #define XVIP_ENCODING_NBITS_MASK … #define XVIP_ENCODING_NBITS_SHIFT … #define XVIP_ENCODING_VIDEO_FORMAT_YUV422 … #define XVIP_ENCODING_VIDEO_FORMAT_YUV444 … #define XVIP_ENCODING_VIDEO_FORMAT_RGB … #define XVIP_ENCODING_VIDEO_FORMAT_YUV420 … #define XVIP_ENCODING_VIDEO_FORMAT_MASK … #define XVIP_ENCODING_VIDEO_FORMAT_SHIFT … /** * struct xvip_device - Xilinx Video IP device structure * @subdev: V4L2 subdevice * @dev: (OF) device * @iomem: device I/O register space remapped to kernel virtual memory * @clk: video core clock * @saved_ctrl: saved control register for resume / suspend */ struct xvip_device { … }; /** * struct xvip_video_format - Xilinx Video IP video format description * @vf_code: AXI4 video format code * @width: AXI4 format width in bits per component * @pattern: CFA pattern for Mono/Sensor formats * @code: media bus format code * @bpp: bytes per pixel (when stored in memory) * @fourcc: V4L2 pixel format FCC identifier */ struct xvip_video_format { … }; const struct xvip_video_format *xvip_get_format_by_code(unsigned int code); const struct xvip_video_format *xvip_get_format_by_fourcc(u32 fourcc); const struct xvip_video_format *xvip_of_get_format(struct device_node *node); void xvip_set_format_size(struct v4l2_mbus_framefmt *format, const struct v4l2_subdev_format *fmt); int xvip_enum_mbus_code(struct v4l2_subdev *subdev, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code); int xvip_enum_frame_size(struct v4l2_subdev *subdev, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_size_enum *fse); static inline u32 xvip_read(struct xvip_device *xvip, u32 addr) { … } static inline void xvip_write(struct xvip_device *xvip, u32 addr, u32 value) { … } static inline void xvip_clr(struct xvip_device *xvip, u32 addr, u32 clr) { … } static inline void xvip_set(struct xvip_device *xvip, u32 addr, u32 set) { … } void xvip_clr_or_set(struct xvip_device *xvip, u32 addr, u32 mask, bool set); void xvip_clr_and_set(struct xvip_device *xvip, u32 addr, u32 clr, u32 set); int xvip_init_resources(struct xvip_device *xvip); void xvip_cleanup_resources(struct xvip_device *xvip); static inline void xvip_reset(struct xvip_device *xvip) { … } static inline void xvip_start(struct xvip_device *xvip) { … } static inline void xvip_stop(struct xvip_device *xvip) { … } static inline void xvip_resume(struct xvip_device *xvip) { … } static inline void xvip_suspend(struct xvip_device *xvip) { … } static inline void xvip_set_frame_size(struct xvip_device *xvip, const struct v4l2_mbus_framefmt *format) { … } static inline void xvip_get_frame_size(struct xvip_device *xvip, struct v4l2_mbus_framefmt *format) { … } static inline void xvip_enable_reg_update(struct xvip_device *xvip) { … } static inline void xvip_disable_reg_update(struct xvip_device *xvip) { … } static inline void xvip_print_version(struct xvip_device *xvip) { … } #endif /* __XILINX_VIP_H__ */
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