/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * cx18 ADEC header * * Derived from cx25840-core.h * * Copyright (C) 2007 Hans Verkuil <[email protected]> * Copyright (C) 2008 Andy Walls <[email protected]> */ #ifndef _CX18_AV_CORE_H_ #define _CX18_AV_CORE_H_ #include <media/v4l2-device.h> #include <media/v4l2-ctrls.h> struct cx18; enum cx18_av_video_input { … }; enum cx18_av_audio_input { … }; struct cx18_av_state { … }; /* Registers */ #define CXADEC_CHIP_TYPE_TIGER … #define CXADEC_CHIP_TYPE_MAKO … #define CXADEC_HOST_REG1 … #define CXADEC_HOST_REG2 … #define CXADEC_CHIP_CTRL … #define CXADEC_AFE_CTRL … #define CXADEC_PLL_CTRL1 … #define CXADEC_VID_PLL_FRAC … #define CXADEC_AUX_PLL_FRAC … #define CXADEC_PIN_CTRL1 … #define CXADEC_PIN_CTRL2 … #define CXADEC_PIN_CFG1 … #define CXADEC_PIN_CFG2 … #define CXADEC_PIN_CFG3 … #define CXADEC_I2S_MCLK … #define CXADEC_AUD_LOCK1 … #define CXADEC_AUD_LOCK2 … #define CXADEC_POWER_CTRL … #define CXADEC_AFE_DIAG_CTRL1 … #define CXADEC_AFE_DIAG_CTRL2 … #define CXADEC_AFE_DIAG_CTRL3 … #define CXADEC_PLL_DIAG_CTRL … #define CXADEC_TEST_CTRL1 … #define CXADEC_TEST_CTRL2 … #define CXADEC_BIST_STAT … #define CXADEC_DLL1_DIAG_CTRL … #define CXADEC_DLL2_DIAG_CTRL … /* IR registers */ #define CXADEC_IR_CTRL_REG … #define CXADEC_IR_TXCLK_REG … #define CXADEC_IR_RXCLK_REG … #define CXADEC_IR_CDUTY_REG … #define CXADEC_IR_STAT_REG … #define CXADEC_IR_IRQEN_REG … #define CXADEC_IR_FILTER_REG … #define CXADEC_IR_FIFO_REG … /* Video Registers */ #define CXADEC_MODE_CTRL … #define CXADEC_OUT_CTRL1 … #define CXADEC_OUT_CTRL2 … #define CXADEC_GEN_STAT … #define CXADEC_INT_STAT_MASK … #define CXADEC_LUMA_CTRL … #define CXADEC_BRIGHTNESS_CTRL_BYTE … #define CXADEC_CONTRAST_CTRL_BYTE … #define CXADEC_LUMA_CTRL_BYTE_3 … #define CXADEC_HSCALE_CTRL … #define CXADEC_VSCALE_CTRL … #define CXADEC_CHROMA_CTRL … #define CXADEC_USAT_CTRL_BYTE … #define CXADEC_VSAT_CTRL_BYTE … #define CXADEC_HUE_CTRL_BYTE … #define CXADEC_VBI_LINE_CTRL1 … #define CXADEC_VBI_LINE_CTRL2 … #define CXADEC_VBI_LINE_CTRL3 … #define CXADEC_VBI_LINE_CTRL4 … #define CXADEC_VBI_LINE_CTRL5 … #define CXADEC_VBI_FC_CFG … #define CXADEC_VBI_MISC_CFG1 … #define CXADEC_VBI_MISC_CFG2 … #define CXADEC_VBI_PAY1 … #define CXADEC_VBI_PAY2 … #define CXADEC_VBI_CUST1_CFG1 … #define CXADEC_VBI_CUST1_CFG2 … #define CXADEC_VBI_CUST1_CFG3 … #define CXADEC_VBI_CUST2_CFG1 … #define CXADEC_VBI_CUST2_CFG2 … #define CXADEC_VBI_CUST2_CFG3 … #define CXADEC_VBI_CUST3_CFG1 … #define CXADEC_VBI_CUST3_CFG2 … #define CXADEC_VBI_CUST3_CFG3 … #define CXADEC_HORIZ_TIM_CTRL … #define CXADEC_VERT_TIM_CTRL … #define CXADEC_SRC_COMB_CFG … #define CXADEC_CHROMA_VBIOFF_CFG … #define CXADEC_FIELD_COUNT … #define CXADEC_MISC_TIM_CTRL … #define CXADEC_DFE_CTRL1 … #define CXADEC_DFE_CTRL2 … #define CXADEC_DFE_CTRL3 … #define CXADEC_PLL_CTRL2 … #define CXADEC_HTL_CTRL … #define CXADEC_COMB_CTRL … #define CXADEC_CRUSH_CTRL … #define CXADEC_SOFT_RST_CTRL … #define CXADEC_MV_DT_CTRL2 … #define CXADEC_MV_DT_CTRL3 … #define CXADEC_MISC_DIAG_CTRL … #define CXADEC_DL_CTL … #define CXADEC_DL_CTL_ADDRESS_LOW … #define CXADEC_DL_CTL_ADDRESS_HIGH … #define CXADEC_DL_CTL_DATA … #define CXADEC_DL_CTL_CONTROL … #define CXADEC_STD_DET_STATUS … #define CXADEC_STD_DET_CTL … #define CXADEC_STD_DET_CTL_AUD_CTL … #define CXADEC_STD_DET_CTL_PREF_MODE … #define CXADEC_DW8051_INT … #define CXADEC_GENERAL_CTL … #define CXADEC_AAGC_CTL … #define CXADEC_IF_SRC_CTL … #define CXADEC_ANLOG_DEMOD_CTL … #define CXADEC_ROT_FREQ_CTL … #define CXADEC_FM1_CTL … #define CXADEC_PDF_CTL … #define CXADEC_DFT1_CTL1 … #define CXADEC_DFT1_CTL2 … #define CXADEC_DFT_STATUS … #define CXADEC_DFT2_CTL1 … #define CXADEC_DFT2_CTL2 … #define CXADEC_DFT2_STATUS … #define CXADEC_DFT3_CTL1 … #define CXADEC_DFT3_CTL2 … #define CXADEC_DFT3_STATUS … #define CXADEC_DFT4_CTL1 … #define CXADEC_DFT4_CTL2 … #define CXADEC_DFT4_STATUS … #define CXADEC_AM_MTS_DET … #define CXADEC_ANALOG_MUX_CTL … #define CXADEC_DIG_PLL_CTL1 … #define CXADEC_DIG_PLL_CTL2 … #define CXADEC_DIG_PLL_CTL3 … #define CXADEC_DIG_PLL_CTL4 … #define CXADEC_DIG_PLL_CTL5 … #define CXADEC_DEEMPH_GAIN_CTL … #define CXADEC_DEEMPH_COEF1 … #define CXADEC_DEEMPH_COEF2 … #define CXADEC_DBX1_CTL1 … #define CXADEC_DBX1_CTL2 … #define CXADEC_DBX1_STATUS … #define CXADEC_DBX2_CTL1 … #define CXADEC_DBX2_CTL2 … #define CXADEC_DBX2_STATUS … #define CXADEC_AM_FM_DIFF … /* NICAM registers go here */ #define CXADEC_NICAM_STATUS … #define CXADEC_DEMATRIX_CTL … #define CXADEC_PATH1_CTL1 … #define CXADEC_PATH1_VOL_CTL … #define CXADEC_PATH1_EQ_CTL … #define CXADEC_PATH1_SC_CTL … #define CXADEC_PATH2_CTL1 … #define CXADEC_PATH2_VOL_CTL … #define CXADEC_PATH2_EQ_CTL … #define CXADEC_PATH2_SC_CTL … #define CXADEC_SRC_CTL … #define CXADEC_SRC_LF_COEF … #define CXADEC_SRC1_CTL … #define CXADEC_SRC2_CTL … #define CXADEC_SRC3_CTL … #define CXADEC_SRC4_CTL … #define CXADEC_SRC5_CTL … #define CXADEC_SRC6_CTL … #define CXADEC_BASEBAND_OUT_SEL … #define CXADEC_I2S_IN_CTL … #define CXADEC_I2S_OUT_CTL … #define CXADEC_AC97_CTL … #define CXADEC_QAM_PDF … #define CXADEC_QAM_CONST_DEC … #define CXADEC_QAM_ROTATOR_FREQ … /* Bit definitions / settings used in Mako Audio */ #define CXADEC_PREF_MODE_MONO_LANGA … #define CXADEC_PREF_MODE_MONO_LANGB … #define CXADEC_PREF_MODE_MONO_LANGC … #define CXADEC_PREF_MODE_FALLBACK … #define CXADEC_PREF_MODE_STEREO … #define CXADEC_PREF_MODE_DUAL_LANG_AC … #define CXADEC_PREF_MODE_DUAL_LANG_BC … #define CXADEC_PREF_MODE_DUAL_LANG_AB … #define CXADEC_DETECT_STEREO … #define CXADEC_DETECT_DUAL … #define CXADEC_DETECT_TRI … #define CXADEC_DETECT_SAP … #define CXADEC_DETECT_NO_SIGNAL … #define CXADEC_SELECT_AUDIO_STANDARD_BG … #define CXADEC_SELECT_AUDIO_STANDARD_DK1 … #define CXADEC_SELECT_AUDIO_STANDARD_DK2 … #define CXADEC_SELECT_AUDIO_STANDARD_DK3 … #define CXADEC_SELECT_AUDIO_STANDARD_I … #define CXADEC_SELECT_AUDIO_STANDARD_L … #define CXADEC_SELECT_AUDIO_STANDARD_BTSC … #define CXADEC_SELECT_AUDIO_STANDARD_EIAJ … #define CXADEC_SELECT_AUDIO_STANDARD_A2_M … #define CXADEC_SELECT_AUDIO_STANDARD_FM … #define CXADEC_SELECT_AUDIO_STANDARD_AUTO … static inline struct cx18_av_state *to_cx18_av_state(struct v4l2_subdev *sd) { … } static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) { … } /* ----------------------------------------------------------------------- */ /* cx18_av-core.c */ int cx18_av_write(struct cx18 *cx, u16 addr, u8 value); int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value); int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value); int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask); int cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask); u8 cx18_av_read(struct cx18 *cx, u16 addr); u32 cx18_av_read4(struct cx18 *cx, u16 addr); int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value); int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value); void cx18_av_std_setup(struct cx18 *cx); int cx18_av_probe(struct cx18 *cx); /* ----------------------------------------------------------------------- */ /* cx18_av-firmware.c */ int cx18_av_loadfw(struct cx18 *cx); /* ----------------------------------------------------------------------- */ /* cx18_av-audio.c */ int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq); void cx18_av_audio_set_path(struct cx18 *cx); extern const struct v4l2_ctrl_ops cx18_av_audio_ctrl_ops; /* ----------------------------------------------------------------------- */ /* cx18_av-vbi.c */ int cx18_av_decode_vbi_line(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi); int cx18_av_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt); int cx18_av_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt); int cx18_av_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt); #endif
Codebase Browser
linux