/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * cx18 System Control Block initialization * * Copyright (C) 2007 Hans Verkuil <[email protected]> * Copyright (C) 2008 Andy Walls <[email protected]> */ #ifndef CX18_SCB_H #define CX18_SCB_H #include "cx18-mailbox.h" /* NOTE: All ACK interrupts are in the SW2 register. All non-ACK interrupts are in the SW1 register. */ #define IRQ_APU_TO_CPU … #define IRQ_CPU_TO_APU_ACK … #define IRQ_HPU_TO_CPU … #define IRQ_CPU_TO_HPU_ACK … #define IRQ_PPU_TO_CPU … #define IRQ_CPU_TO_PPU_ACK … #define IRQ_EPU_TO_CPU … #define IRQ_CPU_TO_EPU_ACK … #define IRQ_CPU_TO_APU … #define IRQ_APU_TO_CPU_ACK … #define IRQ_HPU_TO_APU … #define IRQ_APU_TO_HPU_ACK … #define IRQ_PPU_TO_APU … #define IRQ_APU_TO_PPU_ACK … #define IRQ_EPU_TO_APU … #define IRQ_APU_TO_EPU_ACK … #define IRQ_CPU_TO_HPU … #define IRQ_HPU_TO_CPU_ACK … #define IRQ_APU_TO_HPU … #define IRQ_HPU_TO_APU_ACK … #define IRQ_PPU_TO_HPU … #define IRQ_HPU_TO_PPU_ACK … #define IRQ_EPU_TO_HPU … #define IRQ_HPU_TO_EPU_ACK … #define IRQ_CPU_TO_PPU … #define IRQ_PPU_TO_CPU_ACK … #define IRQ_APU_TO_PPU … #define IRQ_PPU_TO_APU_ACK … #define IRQ_HPU_TO_PPU … #define IRQ_PPU_TO_HPU_ACK … #define IRQ_EPU_TO_PPU … #define IRQ_PPU_TO_EPU_ACK … #define IRQ_CPU_TO_EPU … #define IRQ_EPU_TO_CPU_ACK … #define IRQ_APU_TO_EPU … #define IRQ_EPU_TO_APU_ACK … #define IRQ_HPU_TO_EPU … #define IRQ_EPU_TO_HPU_ACK … #define IRQ_PPU_TO_EPU … #define IRQ_EPU_TO_PPU_ACK … #define SCB_OFFSET … /* If Firmware uses fixed memory map, it shall not allocate the area between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */ #define SCB_RESERVED_SIZE … /* This structure is used by EPU to provide memory descriptors in its memory */ struct cx18_mdl_ent { … }; struct cx18_scb { … }; void cx18_init_scb(struct cx18 *cx); #endif
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