/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Driver for the Conexant CX23885 PCIe bridge * * Copyright (c) 2006 Steven Toth <[email protected]> */ #ifndef _CX23885_REG_H_ #define _CX23885_REG_H_ /* Address Map 0x00000000 -> 0x00009000 TX SRAM (Fifos) 0x00010000 -> 0x00013c00 RX SRAM CMDS + CDT EACH CMDS struct is 0x80 bytes long DMAx_PTR1 = 0x03040 address of first cluster DMAx_PTR2 = 0x10600 address of the CDT DMAx_CNT1 = cluster size in (bytes >> 4) -1 DMAx_CNT2 = total cdt size for all entries >> 3 Cluster Descriptor entry = 4 DWORDS DWORD 0 -> ptr to cluster DWORD 1 Reserved DWORD 2 Reserved DWORD 3 Reserved Channel manager Data Structure entry = 20 DWORD 0 IntialProgramCounterLow 1 IntialProgramCounterHigh 2 ClusterDescriptorTableBase 3 ClusterDescriptorTableSize 4 InstructionQueueBase 5 InstructionQueueSize ... Reserved 19 Reserved */ /* Risc Instructions */ #define RISC_CNT_INC … #define RISC_CNT_RESET … #define RISC_IRQ1 … #define RISC_IRQ2 … #define RISC_EOL … #define RISC_SOL … #define RISC_WRITE … #define RISC_SKIP … #define RISC_JUMP … #define RISC_SYNC … #define RISC_RESYNC … #define RISC_READ … #define RISC_WRITERM … #define RISC_WRITECM … #define RISC_WRITECR … #define RISC_WRITEC … #define RISC_READC … /* Audio and Video Core */ #define HOST_REG1 … #define HOST_REG2 … #define HOST_REG3 … /* Chip Configuration Registers */ #define CHIP_CTRL … #define AFE_CTRL … #define VID_PLL_INT_POST … #define VID_PLL_FRAC … #define AUX_PLL_INT_POST … #define AUX_PLL_FRAC … #define SYS_PLL_INT_POST … #define SYS_PLL_FRAC … #define PIN_CTRL … #define AUD_IO_CTRL … #define AUD_LOCK1 … #define AUD_LOCK2 … #define POWER_CTRL … #define AFE_DIAG_CTRL1 … #define AFE_DIAG_CTRL3 … #define PLL_DIAG_CTRL … #define AFE_CLK_OUT_CTRL … #define DLL1_DIAG_CTRL … /* GPIO[23:19] Output Enable */ #define GPIO2_OUT_EN_REG … /* GPIO[23:19] Data Registers */ #define GPIO2 … #define IFADC_CTRL … /* Infrared Remote Registers */ #define IR_CNTRL_REG … #define IR_TXCLK_REG … #define IR_RXCLK_REG … #define IR_CDUTY_REG … #define IR_STAT_REG … #define IR_IRQEN_REG … #define IR_FILTR_REG … #define IR_FIFO_REG … /* Video Decoder Registers */ #define MODE_CTRL … #define OUT_CTRL1 … #define OUT_CTRL2 … #define GEN_STAT … #define INT_STAT_MASK … #define LUMA_CTRL … #define HSCALE_CTRL … #define VSCALE_CTRL … #define CHROMA_CTRL … #define VBI_LINE_CTRL1 … #define VBI_LINE_CTRL2 … #define VBI_LINE_CTRL3 … #define VBI_LINE_CTRL4 … #define VBI_LINE_CTRL5 … #define VBI_FC_CFG … #define VBI_MISC_CFG1 … #define VBI_MISC_CFG2 … #define VBI_PAY1 … #define VBI_PAY2 … #define VBI_CUST1_CFG1 … #define VBI_CUST1_CFG2 … #define VBI_CUST1_CFG3 … #define VBI_CUST2_CFG1 … #define VBI_CUST2_CFG2 … #define VBI_CUST2_CFG3 … #define VBI_CUST3_CFG1 … #define VBI_CUST3_CFG2 … #define VBI_CUST3_CFG3 … #define HORIZ_TIM_CTRL … #define VERT_TIM_CTRL … #define SRC_COMB_CFG … #define CHROMA_VBIOFF_CFG … #define FIELD_COUNT … #define MISC_TIM_CTRL … #define DFE_CTRL1 … #define DFE_CTRL2 … #define DFE_CTRL3 … #define PLL_CTRL … #define HTL_CTRL … #define COMB_CTRL … #define CRUSH_CTRL … #define SOFT_RST_CTRL … #define CX885_VERSION … #define VBI_PASS_CTRL … /* Audio Decoder Registers */ /* 8051 Configuration */ #define DL_CTL … #define STD_DET_STATUS … #define STD_DET_CTL … #define DW8051_INT … #define GENERAL_CTL … #define AAGC_CTL … #define DEMATRIX_CTL … #define PATH1_CTL1 … #define PATH1_VOL_CTL … #define PATH1_EQ_CTL … #define PATH1_SC_CTL … #define PATH2_CTL1 … #define PATH2_VOL_CTL … #define PATH2_EQ_CTL … #define PATH2_SC_CTL … /* Sample Rate Converter */ #define SRC_CTL … #define SRC_LF_COEF … #define SRC1_CTL … #define SRC2_CTL … #define SRC3_CTL … #define SRC4_CTL … #define SRC5_CTL … #define SRC6_CTL … #define BAND_OUT_SEL … #define I2S_N_CTL … #define I2S_OUT_CTL … #define AUTOCONFIG_REG … /* Audio ADC Registers */ #define DSM_CTRL1 … #define DSM_CTRL2 … #define CHP_EN_CTRL … #define CHP_CLK_CTRL1 … #define CHP_CLK_CTRL2 … #define BG_REF_CTRL … #define SD2_SW_CTRL1 … #define SD2_SW_CTRL2 … #define SD2_BIAS_CTRL … #define AMP_BIAS_CTRL … #define CH_PWR_CTRL1 … #define FLD_CH_SEL … #define CH_PWR_CTRL2 … #define DSM_STATUS1 … #define DSM_STATUS2 … #define DIG_CTL1 … #define DIG_CTL2 … #define I2S_TX_CFG … #define DEV_CNTRL2 … #define PCI_MSK_IR … #define PCI_MSK_AV_CORE … #define PCI_MSK_GPIO1 … #define PCI_MSK_GPIO0 … #define PCI_MSK_APB_DMA … #define PCI_MSK_AL_WR … #define PCI_MSK_AL_RD … #define PCI_MSK_RISC_WR … #define PCI_MSK_RISC_RD … #define PCI_MSK_AUD_EXT … #define PCI_MSK_AUD_INT … #define PCI_MSK_VID_C … #define PCI_MSK_VID_B … #define PCI_MSK_VID_A … #define PCI_INT_MSK … #define PCI_INT_STAT … #define PCI_INT_MSTAT … #define VID_A_INT_MSK … #define VID_A_INT_STAT … #define VID_A_INT_MSTAT … #define VID_A_INT_SSTAT … #define VID_B_INT_MSK … #define VID_B_MSK_BAD_PKT … #define VID_B_MSK_VBI_OPC_ERR … #define VID_B_MSK_OPC_ERR … #define VID_B_MSK_VBI_SYNC … #define VID_B_MSK_SYNC … #define VID_B_MSK_VBI_OF … #define VID_B_MSK_OF … #define VID_B_MSK_VBI_RISCI2 … #define VID_B_MSK_RISCI2 … #define VID_B_MSK_VBI_RISCI1 … #define VID_B_MSK_RISCI1 … #define VID_B_INT_STAT … #define VID_B_INT_MSTAT … #define VID_B_INT_SSTAT … #define VID_B_MSK_BAD_PKT … #define VID_B_MSK_OPC_ERR … #define VID_B_MSK_SYNC … #define VID_B_MSK_OF … #define VID_B_MSK_RISCI2 … #define VID_B_MSK_RISCI1 … #define VID_C_MSK_BAD_PKT … #define VID_C_MSK_OPC_ERR … #define VID_C_MSK_SYNC … #define VID_C_MSK_OF … #define VID_C_MSK_RISCI2 … #define VID_C_MSK_RISCI1 … /* A superset for testing purposes */ #define VID_BC_MSK_BAD_PKT … #define VID_BC_MSK_OPC_ERR … #define VID_BC_MSK_SYNC … #define VID_BC_MSK_OF … #define VID_BC_MSK_VBI_RISCI2 … #define VID_BC_MSK_RISCI2 … #define VID_BC_MSK_VBI_RISCI1 … #define VID_BC_MSK_RISCI1 … #define VID_C_INT_MSK … #define VID_C_INT_STAT … #define VID_C_INT_MSTAT … #define VID_C_INT_SSTAT … #define AUDIO_INT_INT_MSK … #define AUDIO_INT_INT_STAT … #define AUDIO_INT_INT_MSTAT … #define AUDIO_INT_INT_SSTAT … #define AUDIO_EXT_INT_MSK … #define AUDIO_EXT_INT_STAT … #define AUDIO_EXT_INT_MSTAT … #define AUDIO_EXT_INT_SSTAT … /* Bits [7:0] set in both TC_REQ and TC_REQ_SET * indicate a stall in the RISC engine for a * particular rider traffic class. This causes * the 885 and 888 bridges (unknown about 887) * to become inoperable. Setting bits in * TC_REQ_SET resets the corresponding bits * in TC_REQ (and TC_REQ_SET) allowing * operation to continue. */ #define TC_REQ … #define TC_REQ_SET … #define RDR_CFG0 … #define RDR_CFG1 … #define RDR_CFG2 … #define RDR_RDRCTL1 … #define RDR_TLCTL0 … /* APB DMAC Current Buffer Pointer */ #define DMA1_PTR1 … #define DMA2_PTR1 … #define DMA3_PTR1 … #define DMA4_PTR1 … #define DMA5_PTR1 … #define DMA6_PTR1 … #define DMA7_PTR1 … #define DMA8_PTR1 … /* APB DMAC Current Table Pointer */ #define DMA1_PTR2 … #define DMA2_PTR2 … #define DMA3_PTR2 … #define DMA4_PTR2 … #define DMA5_PTR2 … #define DMA6_PTR2 … #define DMA7_PTR2 … #define DMA8_PTR2 … /* APB DMAC Buffer Limit */ #define DMA1_CNT1 … #define DMA2_CNT1 … #define DMA3_CNT1 … #define DMA4_CNT1 … #define DMA5_CNT1 … #define DMA6_CNT1 … #define DMA7_CNT1 … #define DMA8_CNT1 … /* APB DMAC Table Size */ #define DMA1_CNT2 … #define DMA2_CNT2 … #define DMA3_CNT2 … #define DMA4_CNT2 … #define DMA5_CNT2 … #define DMA6_CNT2 … #define DMA7_CNT2 … #define DMA8_CNT2 … /* Timer Counters */ #define TM_CNT_LDW … #define TM_CNT_UW … #define TM_LMT_LDW … #define TM_LMT_UW … /* GPIO */ #define GP0_IO … #define GPIO_ISM … #define SOFT_RESET … /* GPIO (417 Microsoftcontroller) RW Data */ #define MC417_RWD … /* GPIO (417 Microsoftcontroller) Output Enable, Low Active */ #define MC417_OEN … #define MC417_CTL … #define ALT_PIN_OUT_SEL … #define CLK_DELAY … #define PAD_CTRL … /* Video A Interface */ #define VID_A_GPCNT … #define VBI_A_GPCNT … #define VID_A_GPCNT_CTL … #define VBI_A_GPCNT_CTL … #define VID_A_DMA_CTL … #define VID_A_VIP_CTRL … #define VID_A_PIXEL_FRMT … #define VID_A_VBI_CTRL … /* Video B Interface */ #define VID_B_DMA … #define VBI_B_DMA … #define VID_B_GPCNT … #define VBI_B_GPCNT … #define VID_B_GPCNT_CTL … #define VBI_B_GPCNT_CTL … #define VID_B_DMA_CTL … #define VID_B_SRC_SEL … #define VID_B_LNGTH … #define VID_B_HW_SOP_CTL … #define VID_B_GEN_CTL … #define VID_B_BD_PKT_STATUS … #define VID_B_SOP_STATUS … #define VID_B_FIFO_OVFL_STAT … #define VID_B_VLD_MISC … #define VID_B_TS_CLK_EN … #define VID_B_VIP_CTRL … #define VID_B_PIXEL_FRMT … /* Video C Interface */ #define VID_C_DMA … #define VBI_C_DMA … #define VID_C_GPCNT … #define VID_C_GPCNT_CTL … #define VBI_C_GPCNT_CTL … #define VID_C_DMA_CTL … #define VID_C_LNGTH … #define VID_C_HW_SOP_CTL … #define VID_C_GEN_CTL … #define VID_C_BD_PKT_STATUS … #define VID_C_SOP_STATUS … #define VID_C_FIFO_OVFL_STAT … #define VID_C_VLD_MISC … #define VID_C_TS_CLK_EN … /* Internal Audio Interface */ #define AUD_INT_A_GPCNT … #define AUD_INT_B_GPCNT … #define AUD_INT_A_GPCNT_CTL … #define AUD_INT_B_GPCNT_CTL … #define AUD_INT_DMA_CTL … #define AUD_INT_A_LNGTH … #define AUD_INT_B_LNGTH … #define AUD_INT_A_MODE … #define AUD_INT_B_MODE … /* External Audio Interface */ #define AUD_EXT_DMA … #define AUD_EXT_GPCNT … #define AUD_EXT_GPCNT_CTL … #define AUD_EXT_DMA_CTL … #define AUD_EXT_LNGTH … #define AUD_EXT_A_MODE … /* I2C Bus 1 */ #define I2C1_ADDR … #define I2C1_WDATA … #define I2C1_CTRL … #define I2C1_RDATA … #define I2C1_STAT … /* I2C Bus 2 */ #define I2C2_ADDR … #define I2C2_WDATA … #define I2C2_CTRL … #define I2C2_RDATA … #define I2C2_STAT … /* I2C Bus 3 */ #define I2C3_ADDR … #define I2C3_WDATA … #define I2C3_CTRL … #define I2C3_RDATA … #define I2C3_STAT … /* UART */ #define UART_CTL … #define UART_BRD … #define UART_ISR … #define UART_CNT … #endif /* _CX23885_REG_H_ */
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