/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Driver for the Conexant CX25821 PCIe bridge * * Copyright (C) 2009 Conexant Systems Inc. * Authors <[email protected]>, <[email protected]> */ #ifndef __ATHENA_SRAM_H__ #define __ATHENA_SRAM_H__ /* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */ #define VID_CMDS_SIZE … #define AUDIO_CMDS_SIZE … #define MBIF_CMDS_SIZE … /* #define RX_SRAM_POOL_START_SIZE = 0; // Start of usable RX SRAM for buffers */ #define VID_IQ_SIZE … #define MBIF_IQ_SIZE … #define AUDIO_IQ_SIZE … #define VID_CDT_SIZE … #define MBIF_CDT_SIZE … #define AUDIO_CDT_SIZE … /* #define RX_SRAM_POOL_FREE_SIZE = 16; // Start of available RX SRAM */ /* #define RX_SRAM_END_SIZE = 0; // End of RX SRAM */ /* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */ /* #define MSI_DATA_SIZE = 64; // Reserved (MSI Data, RISC working stora */ #define VID_CLUSTER_SIZE … #define AUDIO_CLUSTER_SIZE … #define MBIF_CLUSTER_SIZE … /* #define TX_SRAM_POOL_FREE_SIZE = 704; // Start of available TX SRAM */ /* #define TX_SRAM_END_SIZE = 0; // End of TX SRAM */ /* Receive SRAM */ #define RX_SRAM_START … #define VID_A_DOWN_CMDS … #define VID_B_DOWN_CMDS … #define VID_C_DOWN_CMDS … #define VID_D_DOWN_CMDS … #define VID_E_DOWN_CMDS … #define VID_F_DOWN_CMDS … #define VID_G_DOWN_CMDS … #define VID_H_DOWN_CMDS … #define VID_A_UP_CMDS … #define VID_B_UP_CMDS … #define VID_C_UP_CMDS … #define VID_D_UP_CMDS … #define VID_E_UP_CMDS … #define VID_F_UP_CMDS … #define VID_I_UP_CMDS … #define VID_J_UP_CMDS … #define AUD_A_DOWN_CMDS … #define AUD_B_DOWN_CMDS … #define AUD_C_DOWN_CMDS … #define AUD_D_DOWN_CMDS … #define AUD_A_UP_CMDS … #define AUD_B_UP_CMDS … #define AUD_C_UP_CMDS … #define AUD_E_UP_CMDS … #define MBIF_A_DOWN_CMDS … #define MBIF_B_DOWN_CMDS … #define DMA_SCRATCH_PAD … /* #define RX_SRAM_POOL_START = 0x105B0; */ #define VID_A_IQ … #define VID_B_IQ … #define VID_C_IQ … #define VID_D_IQ … #define VID_E_IQ … #define VID_F_IQ … #define VID_G_IQ … #define VID_H_IQ … #define VID_I_IQ … #define VID_J_IQ … #define AUD_A_IQ … #define AUD_B_IQ … #define AUD_C_IQ … #define AUD_D_IQ … #define AUD_E_IQ … #define MBIF_A_IQ … #define MBIF_B_IQ … #define VID_A_CDT … #define VID_B_CDT … #define VID_C_CDT … #define VID_D_CDT … #define VID_E_CDT … #define VID_F_CDT … #define VID_G_CDT … #define VID_H_CDT … #define VID_I_CDT … #define VID_J_CDT … #define AUD_A_CDT … #define AUD_B_CDT … #define AUD_C_CDT … #define AUD_D_CDT … #define AUD_E_CDT … #define MBIF_A_CDT … #define MBIF_B_CDT … /* Cluster Buffer for RX */ #define VID_A_UP_CLUSTER_1 … #define VID_A_UP_CLUSTER_2 … #define VID_A_UP_CLUSTER_3 … #define VID_A_UP_CLUSTER_4 … #define VID_B_UP_CLUSTER_1 … #define VID_B_UP_CLUSTER_2 … #define VID_B_UP_CLUSTER_3 … #define VID_B_UP_CLUSTER_4 … #define VID_C_UP_CLUSTER_1 … #define VID_C_UP_CLUSTER_2 … #define VID_C_UP_CLUSTER_3 … #define VID_C_UP_CLUSTER_4 … #define VID_D_UP_CLUSTER_1 … #define VID_D_UP_CLUSTER_2 … #define VID_D_UP_CLUSTER_3 … #define VID_D_UP_CLUSTER_4 … #define VID_E_UP_CLUSTER_1 … #define VID_E_UP_CLUSTER_2 … #define VID_E_UP_CLUSTER_3 … #define VID_E_UP_CLUSTER_4 … #define VID_F_UP_CLUSTER_1 … #define VID_F_UP_CLUSTER_2 … #define VID_F_UP_CLUSTER_3 … #define VID_F_UP_CLUSTER_4 … #define VID_I_UP_CLUSTER_1 … #define VID_I_UP_CLUSTER_2 … #define VID_I_UP_CLUSTER_3 … #define VID_I_UP_CLUSTER_4 … #define VID_J_UP_CLUSTER_1 … #define VID_J_UP_CLUSTER_2 … #define VID_J_UP_CLUSTER_3 … #define VID_J_UP_CLUSTER_4 … #define AUD_A_UP_CLUSTER_1 … #define AUD_A_UP_CLUSTER_2 … #define AUD_A_UP_CLUSTER_3 … #define AUD_B_UP_CLUSTER_1 … #define AUD_B_UP_CLUSTER_2 … #define AUD_B_UP_CLUSTER_3 … #define AUD_C_UP_CLUSTER_1 … #define AUD_C_UP_CLUSTER_2 … #define AUD_C_UP_CLUSTER_3 … #define AUD_E_UP_CLUSTER_1 … #define AUD_E_UP_CLUSTER_2 … #define AUD_E_UP_CLUSTER_3 … #define RX_SRAM_POOL_FREE … #define RX_SRAM_END … /* Free Receive SRAM 144 Bytes */ /* Transmit SRAM */ #define TX_SRAM_POOL_START … #define VID_A_DOWN_CLUSTER_1 … #define VID_A_DOWN_CLUSTER_2 … #define VID_A_DOWN_CLUSTER_3 … #define VID_A_DOWN_CLUSTER_4 … #define VID_B_DOWN_CLUSTER_1 … #define VID_B_DOWN_CLUSTER_2 … #define VID_B_DOWN_CLUSTER_3 … #define VID_B_DOWN_CLUSTER_4 … #define VID_C_DOWN_CLUSTER_1 … #define VID_C_DOWN_CLUSTER_2 … #define VID_C_DOWN_CLUSTER_3 … #define VID_C_DOWN_CLUSTER_4 … #define VID_D_DOWN_CLUSTER_1 … #define VID_D_DOWN_CLUSTER_2 … #define VID_D_DOWN_CLUSTER_3 … #define VID_D_DOWN_CLUSTER_4 … #define VID_E_DOWN_CLUSTER_1 … #define VID_E_DOWN_CLUSTER_2 … #define VID_E_DOWN_CLUSTER_3 … #define VID_E_DOWN_CLUSTER_4 … #define VID_F_DOWN_CLUSTER_1 … #define VID_F_DOWN_CLUSTER_2 … #define VID_F_DOWN_CLUSTER_3 … #define VID_F_DOWN_CLUSTER_4 … #define VID_G_DOWN_CLUSTER_1 … #define VID_G_DOWN_CLUSTER_2 … #define VID_G_DOWN_CLUSTER_3 … #define VID_G_DOWN_CLUSTER_4 … #define VID_H_DOWN_CLUSTER_1 … #define VID_H_DOWN_CLUSTER_2 … #define VID_H_DOWN_CLUSTER_3 … #define VID_H_DOWN_CLUSTER_4 … #define AUD_A_DOWN_CLUSTER_1 … #define AUD_A_DOWN_CLUSTER_2 … #define AUD_A_DOWN_CLUSTER_3 … #define AUD_B_DOWN_CLUSTER_1 … #define AUD_B_DOWN_CLUSTER_2 … #define AUD_B_DOWN_CLUSTER_3 … #define AUD_C_DOWN_CLUSTER_1 … #define AUD_C_DOWN_CLUSTER_2 … #define AUD_C_DOWN_CLUSTER_3 … #define AUD_D_DOWN_CLUSTER_1 … #define AUD_D_DOWN_CLUSTER_2 … #define AUD_D_DOWN_CLUSTER_3 … #define TX_SRAM_POOL_FREE … #define TX_SRAM_END … #define BYTES_TO_DWORDS(bcount) … #define BYTES_TO_QWORDS(bcount) … #define BYTES_TO_OWORDS(bcount) … #define VID_IQ_SIZE_DW … #define VID_CDT_SIZE_QW … #define VID_CLUSTER_SIZE_OW … #define AUDIO_IQ_SIZE_DW … #define AUDIO_CDT_SIZE_QW … #define AUDIO_CLUSTER_SIZE_QW … #define MBIF_IQ_SIZE_DW … #define MBIF_CDT_SIZE_QW … #define MBIF_CLUSTER_SIZE_OW … #endif
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