/* SPDX-License-Identifier: GPL-2.0-or-later */ /*************************************************************************** * Copyright (C) 2006-2010 by Marin Mitov * * [email protected] * * * * * ***************************************************************************/ /* DT3155 header file */ #ifndef _DT3155_H_ #define _DT3155_H_ #include <linux/pci.h> #include <linux/interrupt.h> #include <media/v4l2-device.h> #include <media/v4l2-dev.h> #include <media/videobuf2-v4l2.h> #define DT3155_NAME … #define DT3155_VER_MAJ … #define DT3155_VER_MIN … #define DT3155_VER_EXT … #define DT3155_VERSION … /* DT3155 Base Register offsets (memory mapped) */ #define EVEN_DMA_START … #define ODD_DMA_START … #define EVEN_DMA_STRIDE … #define ODD_DMA_STRIDE … #define EVEN_PIXEL_FMT … #define ODD_PIXEL_FMT … #define FIFO_TRIGGER … #define XFER_MODE … #define CSR1 … #define RETRY_WAIT_CNT … #define INT_CSR … #define EVEN_FLD_MASK … #define ODD_FLD_MASK … #define MASK_LENGTH … #define FIFO_FLAG_CNT … #define IIC_CLK_DUR … #define IIC_CSR1 … #define IIC_CSR2 … /* DT3155 Internal Registers indexes (i2c/IIC mapped) */ #define CSR2 … #define EVEN_CSR … #define ODD_CSR … #define CONFIG … #define DT_ID … #define X_CLIP_START … #define Y_CLIP_START … #define X_CLIP_END … #define Y_CLIP_END … #define AD_ADDR … #define AD_LUT … #define AD_CMD … #define DIG_OUT … #define PM_LUT_ADDR … #define PM_LUT_DATA … /* AD command register values */ #define AD_CMD_REG … #define AD_POS_REF … #define AD_NEG_REF … /* CSR1 bit masks */ #define RANGE_EN … #define CRPT_DIS … #define ADDR_ERR_ODD … #define ADDR_ERR_EVEN … #define FLD_CRPT_ODD … #define FLD_CRPT_EVEN … #define FIFO_EN … #define SRST … #define FLD_DN_ODD … #define FLD_DN_EVEN … /* These should not be used. * Use CAP_CONT_ODD/EVEN instead #define CAP_SNGL_ODD 0x00000008 #define CAP_SNGL_EVEN 0x00000004 */ #define CAP_CONT_ODD … #define CAP_CONT_EVEN … /* INT_CSR bit masks */ #define FLD_START_EN … #define FLD_END_ODD_EN … #define FLD_END_EVEN_EN … #define FLD_START … #define FLD_END_ODD … #define FLD_END_EVEN … /* IIC_CSR1 bit masks */ #define DIRECT_ABORT … /* IIC_CSR2 bit masks */ #define NEW_CYCLE … #define DIR_RD … #define IIC_READ … #define IIC_WRITE … /* CSR2 bit masks */ #define DISP_PASS … #define BUSY_ODD … #define BUSY_EVEN … #define SYNC_PRESENT … #define VT_50HZ … #define SYNC_SNTL … #define CHROM_FILT … #define VT_60HZ … /* CSR_EVEN/ODD bit masks */ #define CSR_ERROR … #define CSR_SNGL … #define CSR_DONE … /* CONFIG bit masks */ #define PM_LUT_PGM … #define PM_LUT_SEL … #define CLIP_EN … #define HSCALE_EN … #define EXT_TRIG_UP … #define EXT_TRIG_DOWN … #define ACQ_MODE_NEXT … #define ACQ_MODE_ODD … #define ACQ_MODE_EVEN … /* AD_CMD bit masks */ #define VIDEO_CNL_1 … #define VIDEO_CNL_2 … #define VIDEO_CNL_3 … #define VIDEO_CNL_4 … #define SYNC_CNL_1 … #define SYNC_CNL_2 … #define SYNC_CNL_3 … #define SYNC_CNL_4 … #define SYNC_LVL_1 … #define SYNC_LVL_2 … #define SYNC_LVL_3 … #define SYNC_LVL_4 … /* DT3155 identificator */ #define DT3155_ID … /* per board private data structure */ /** * struct dt3155_priv - private data structure * * @v4l2_dev: v4l2_device structure * @vdev: video_device structure * @pdev: pointer to pci_dev structure * @vidq: vb2_queue structure * @curr_buf: pointer to curren buffer * @mux: mutex to protect the instance * @dmaq: queue for dma buffers * @lock: spinlock for dma queue * @std: input standard * @width: frame width * @height: frame height * @input: current input * @sequence: frame counter * @regs: local copy of mmio base register * @csr2: local copy of csr2 register * @config: local copy of config register */ struct dt3155_priv { … }; #endif /* _DT3155_H_ */
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