/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2001 Jean-Fredric Clere, Nikolas Zimmermann, Georg Acher * Mark Cave-Ayland, Carlo E Prelz, Dick Streefland * Copyright (c) 2002, 2003 Tuukka Toivonen * Copyright (c) 2008 Erik Andrén * Copyright (c) 2008 Chia-I Wu * * P/N 861037: Sensor HDCS1000 ASIC STV0600 * P/N 861050-0010: Sensor HDCS1000 ASIC STV0600 * P/N 861050-0020: Sensor Photobit PB100 ASIC STV0600-1 - QuickCam Express * P/N 861055: Sensor ST VV6410 ASIC STV0610 - LEGO cam * P/N 861075-0040: Sensor HDCS1000 ASIC * P/N 961179-0700: Sensor ST VV6410 ASIC STV0602 - Dexxa WebCam USB * P/N 861040-0000: Sensor ST VV6410 ASIC STV0610 - QuickCam Web */ #ifndef STV06XX_HDCS_H_ #define STV06XX_HDCS_H_ #include "stv06xx_sensor.h" #define HDCS_REG_CONFIG(sd) … #define HDCS_REG_CONTROL(sd) … #define HDCS_1X00_DEF_WIDTH … #define HDCS_1X00_DEF_HEIGHT … #define HDCS_1020_DEF_WIDTH … #define HDCS_1020_DEF_HEIGHT … #define HDCS_1020_BOTTOM_Y_SKIP … #define HDCS_CLK_FREQ_MHZ … #define HDCS_ADC_START_SIG_DUR … /* LSB bit of I2C or register address signifies write (0) or read (1) */ /* I2C Registers common for both HDCS-1000/1100 and HDCS-1020 */ /* Identifications Register */ #define HDCS_IDENT … /* Status Register */ #define HDCS_STATUS … /* Interrupt Mask Register */ #define HDCS_IMASK … /* Pad Control Register */ #define HDCS_PCTRL … /* Pad Drive Control Register */ #define HDCS_PDRV … /* Interface Control Register */ #define HDCS_ICTRL … /* Interface Timing Register */ #define HDCS_ITMG … /* Baud Fraction Register */ #define HDCS_BFRAC … /* Baud Rate Register */ #define HDCS_BRATE … /* ADC Control Register */ #define HDCS_ADCCTRL … /* First Window Row Register */ #define HDCS_FWROW … /* First Window Column Register */ #define HDCS_FWCOL … /* Last Window Row Register */ #define HDCS_LWROW … /* Last Window Column Register */ #define HDCS_LWCOL … /* Timing Control Register */ #define HDCS_TCTRL … /* PGA Gain Register: Even Row, Even Column */ #define HDCS_ERECPGA … /* PGA Gain Register: Even Row, Odd Column */ #define HDCS_EROCPGA … /* PGA Gain Register: Odd Row, Even Column */ #define HDCS_ORECPGA … /* PGA Gain Register: Odd Row, Odd Column */ #define HDCS_OROCPGA … /* Row Exposure Low Register */ #define HDCS_ROWEXPL … /* Row Exposure High Register */ #define HDCS_ROWEXPH … /* I2C Registers only for HDCS-1000/1100 */ /* Sub-Row Exposure Low Register */ #define HDCS00_SROWEXPL … /* Sub-Row Exposure High Register */ #define HDCS00_SROWEXPH … /* Configuration Register */ #define HDCS00_CONFIG … /* Control Register */ #define HDCS00_CONTROL … /* I2C Registers only for HDCS-1020 */ /* Sub-Row Exposure Register */ #define HDCS20_SROWEXP … /* Error Control Register */ #define HDCS20_ERROR … /* Interface Timing 2 Register */ #define HDCS20_ITMG2 … /* Interface Control 2 Register */ #define HDCS20_ICTRL2 … /* Horizontal Blank Register */ #define HDCS20_HBLANK … /* Vertical Blank Register */ #define HDCS20_VBLANK … /* Configuration Register */ #define HDCS20_CONFIG … /* Control Register */ #define HDCS20_CONTROL … #define HDCS_RUN_ENABLE … #define HDCS_SLEEP_MODE … #define HDCS_DEFAULT_EXPOSURE … #define HDCS_DEFAULT_GAIN … static int hdcs_probe_1x00(struct sd *sd); static int hdcs_probe_1020(struct sd *sd); static int hdcs_start(struct sd *sd); static int hdcs_init(struct sd *sd); static int hdcs_init_controls(struct sd *sd); static int hdcs_stop(struct sd *sd); static int hdcs_dump(struct sd *sd); static int hdcs_set_exposure(struct gspca_dev *gspca_dev, __s32 val); static int hdcs_set_gain(struct gspca_dev *gspca_dev, __s32 val); const struct stv06xx_sensor stv06xx_sensor_hdcs1x00 = …; const struct stv06xx_sensor stv06xx_sensor_hdcs1020 = …; static const u16 stv_bridge_init[][2] = …; static const u8 stv_sensor_init[][2] = …; #endif
Codebase Browser
linux