/* SPDX-License-Identifier: GPL-2.0-or-later */ /* cx231xx-reg.h - driver for Conexant Cx23100/101/102 USB video capture devices Copyright (C) 2008 <srinivasa.deevi at conexant dot com> */ #ifndef _CX231XX_REG_H #define _CX231XX_REG_H /***************************************************************************** * VBI codes * *****************************************************************************/ #define SAV_ACTIVE_VIDEO_FIELD1 … #define EAV_ACTIVE_VIDEO_FIELD1 … #define SAV_ACTIVE_VIDEO_FIELD2 … #define EAV_ACTIVE_VIDEO_FIELD2 … #define SAV_VBLANK_FIELD1 … #define EAV_VBLANK_FIELD1 … #define SAV_VBLANK_FIELD2 … #define EAV_VBLANK_FIELD2 … #define SAV_VBI_FIELD1 … #define EAV_VBI_FIELD1 … #define SAV_VBI_FIELD2 … #define EAV_VBI_FIELD2 … /*****************************************************************************/ /* Audio ADC Registers */ #define CH_PWR_CTRL1 … #define CH_PWR_CTRL2 … /*****************************************************************************/ #define HOST_REG1 … #define FLD_FORCE_CHIP_SEL … #define FLD_AUTO_INC_DIS … #define FLD_PREFETCH_EN … /* Reserved [2:3] */ #define FLD_DIGITAL_PWR_DN … #define FLD_SLEEP … /*****************************************************************************/ #define HOST_REG2 … /*****************************************************************************/ #define HOST_REG3 … /*****************************************************************************/ /* added for polaris */ #define GPIO_PIN_CTL0 … #define GPIO_PIN_CTL1 … #define GPIO_PIN_CTL2 … #define GPIO_PIN_CTL3 … #define TS1_PIN_CTL0 … #define TS1_PIN_CTL1 … /*****************************************************************************/ #define FLD_CLK_IN_EN … #define FLD_XTAL_CTRL … #define FLD_BB_CLK_MODE … #define FLD_REF_DIV_PLL … #define FLD_REF_SEL_PLL1 … /*****************************************************************************/ #define CHIP_CTRL … /* Reserved [27] */ /* Reserved [31:21] */ #define FLD_CHIP_ACFG_DIS … /* Reserved [19] */ #define FLD_DUAL_MODE_ADC2 … #define FLD_SIF_EN … #define FLD_SOFT_RST … #define FLD_DEVICE_ID … /*****************************************************************************/ #define AFE_CTRL … #define AFE_CTRL_C2HH_SRC_CTRL … #define FLD_DIF_OUT_SEL … #define FLD_AUX_PLL_CLK_ALT_SEL … #define FLD_UV_ORDER_MODE … #define FLD_FUNC_MODE … #define FLD_ROT1_PHASE_CTL … #define FLD_AUD_IN_SEL … #define FLD_LUMA_IN_SEL … #define FLD_CHROMA_IN_SEL … /* reserve [11:10] */ #define FLD_INV_SPEC_DIS … #define FLD_VGA_SEL_CH3 … #define FLD_VGA_SEL_CH2 … #define FLD_VGA_SEL_CH1 … #define FLD_DCR_BYP_CH1 … #define FLD_DCR_BYP_CH2 … #define FLD_DCR_BYP_CH3 … #define FLD_EN_12DB_CH3 … #define FLD_EN_12DB_CH2 … #define FLD_EN_12DB_CH1 … /* redefine in Cx231xx */ /*****************************************************************************/ #define DC_CTRL1 … /* reserve [31:30] */ #define FLD_CLAMP_LVL_CH1 … #define FLD_CLAMP_LVL_CH2 … /*****************************************************************************/ /*****************************************************************************/ #define DC_CTRL2 … /* reserve [31:28] */ #define FLD_CLAMP_LVL_CH3 … #define FLD_CLAMP_WIND_LENTH … #define FLD_C2HH_SAT_MIN … #define FLD_FLT_BYP_SEL … /*****************************************************************************/ /*****************************************************************************/ #define DC_CTRL3 … /* reserve [31:16] */ #define FLD_ERR_GAIN_CTL … #define FLD_LPF_MIN … /*****************************************************************************/ /*****************************************************************************/ #define DC_CTRL4 … /* reserve [31:31] */ #define FLD_INTG_CH1 … /*****************************************************************************/ /*****************************************************************************/ #define DC_CTRL5 … /* reserve [31:31] */ #define FLD_INTG_CH2 … /*****************************************************************************/ /*****************************************************************************/ #define DC_CTRL6 … /* reserve [31:31] */ #define FLD_INTG_CH3 … /*****************************************************************************/ /*****************************************************************************/ #define PIN_CTRL … #define FLD_OEF_AGC_RF … #define FLD_OEF_AGC_IFVGA … #define FLD_OEF_AGC_IF … #define FLD_REG_BO_PUD … #define FLD_IR_IRQ_STAT … #define FLD_AUD_IRQ_STAT … #define FLD_VID_IRQ_STAT … /* Reserved [27:26] */ #define FLD_IRQ_N_OUT_EN … #define FLD_IRQ_N_POLAR … /* Reserved [23:6] */ #define FLD_OE_AUX_PLL_CLK … #define FLD_OE_I2S_BCLK … #define FLD_OE_I2S_WCLK … #define FLD_OE_AGC_IF … #define FLD_OE_AGC_IFVGA … #define FLD_OE_AGC_RF … /*****************************************************************************/ #define AUD_IO_CTRL … /* Reserved [31:8] */ #define FLD_I2S_PORT_DIR … #define FLD_I2S_OUT_SRC … #define FLD_AUD_CHAN3_SRC … #define FLD_AUD_CHAN2_SRC … #define FLD_AUD_CHAN1_SRC … /*****************************************************************************/ #define AUD_LOCK1 … #define FLD_AUD_LOCK_KI_SHIFT … #define FLD_AUD_LOCK_KD_SHIFT … /* Reserved [27:25] */ #define FLD_EN_AV_LOCK … #define FLD_VID_COUNT … /*****************************************************************************/ #define AUD_LOCK2 … #define FLD_AUD_LOCK_KI_MULT … #define FLD_AUD_LOCK_KD_MULT … /* Reserved [23:22] */ #define FLD_AUD_LOCK_FREQ_SHIFT … #define FLD_AUD_COUNT … /*****************************************************************************/ #define AFE_DIAG_CTRL1 … /* Reserved [31:16] */ #define FLD_CUV_DLY_LENGTH … #define FLD_YC_DLY_LENGTH … /*****************************************************************************/ /* Poalris redefine */ #define AFE_DIAG_CTRL3 … /* Reserved [31:26] */ #define FLD_AUD_DUAL_FLAG_POL … #define FLD_VID_DUAL_FLAG_POL … /* Reserved [23:23] */ #define FLD_COL_CLAMP_DIS_CH1 … #define FLD_COL_CLAMP_DIS_CH2 … #define FLD_COL_CLAMP_DIS_CH3 … #define TEST_CTRL1 … /* Reserved [31:29] */ #define FLD_LBIST_EN … /* Reserved [27:10] */ #define FLD_FI_BIST_INTR_R … #define FLD_FI_BIST_INTR_L … #define FLD_BIST_FAIL_AUD_PLL … #define FLD_BIST_INTR_AUD_PLL … #define FLD_BIST_FAIL_VID_PLL … #define FLD_BIST_INTR_VID_PLL … /* Reserved [3:1] */ #define FLD_CIR_TEST_DIS … /*****************************************************************************/ #define TEST_CTRL2 … #define FLD_TSXCLK_POL_CTL … #define FLD_ISO_CTL_SEL … #define FLD_ISO_CTL_EN … #define FLD_BIST_DEBUGZ … #define FLD_AUD_BIST_TEST_H … /* Reserved [23:22] */ #define FLD_FLTRN_BIST_TEST_H … #define FLD_VID_BIST_TEST_H … /* Reserved [19:17] */ #define FLD_BIST_TEST_H … /* Reserved [15:13] */ #define FLD_TAB_EN … /* Reserved [11:0] */ /*****************************************************************************/ #define BIST_STAT … #define FLD_AUD_BIST_FAIL_H … #define FLD_FLTRN_BIST_FAIL_H … #define FLD_VID_BIST_FAIL_H … #define FLD_AUD_BIST_TST_DONE … #define FLD_FLTRN_BIST_TST_DONE … #define FLD_VID_BIST_TST_DONE … /*****************************************************************************/ /* DirectIF registers definition have been moved to DIF_reg.h */ /*****************************************************************************/ #define MODE_CTRL … #define FLD_AFD_PAL60_DIS … #define FLD_AFD_FORCE_SECAM … #define FLD_AFD_FORCE_PALNC … #define FLD_AFD_FORCE_PAL … #define FLD_AFD_PALM_SEL … #define FLD_CKILL_MODE … #define FLD_COMB_NOTCH_MODE … #define FLD_CLR_LOCK_STAT … #define FLD_FAST_LOCK_MD … #define FLD_WCEN … #define FLD_CAGCEN … #define FLD_CKILLEN … #define FLD_AUTO_SC_LOCK … #define FLD_MAN_SC_FAST_LOCK … #define FLD_INPUT_MODE … #define FLD_AFD_ACQUIRE … #define FLD_AFD_NTSC_SEL … #define FLD_AFD_PAL_SEL … #define FLD_ACFG_DIS … #define FLD_SQ_PIXEL … #define FLD_VID_FMT_SEL … /*****************************************************************************/ #define OUT_CTRL1 … #define FLD_POLAR … /* Reserved [23] */ #define FLD_RND_MODE … #define FLD_VIPCLAMP_EN … #define FLD_VIPBLANK_EN … #define FLD_VIP_OPT_AL … #define FLD_IDID0_SOURCE … #define FLD_DCMODE … #define FLD_CLK_GATING … #define FLD_CLK_INVERT … #define FLD_HSFMT … #define FLD_VALIDFMT … #define FLD_ACTFMT … #define FLD_SWAPRAW … #define FLD_CLAMPRAW_EN … #define FLD_BLUE_FIELD_EN … #define FLD_BLUE_FIELD_ACT … #define FLD_TASKBIT_VAL … #define FLD_ANC_DATA_EN … #define FLD_VBIHACTRAW_EN … #define FLD_MODE10B … #define FLD_OUT_MODE … /*****************************************************************************/ #define OUT_CTRL2 … #define FLD_AUD_GRP … #define FLD_SAMPLE_RATE … #define FLD_AUD_ANC_EN … #define FLD_EN_C … #define FLD_EN_B … #define FLD_EN_A … /* Reserved [23:20] */ #define FLD_IDID1_LSB … #define FLD_IDID0_LSB … #define FLD_IDID1_MSB … #define FLD_IDID0_MSB … /*****************************************************************************/ #define GEN_STAT … #define FLD_VCR_DETECT … #define FLD_SPECIAL_PLAY_N … #define FLD_VPRES … #define FLD_AGC_LOCK … #define FLD_CSC_LOCK … #define FLD_VLOCK … #define FLD_SRC_LOCK … #define FLD_HLOCK … #define FLD_VSYNC_N … #define FLD_SRC_FIFO_UFLOW … #define FLD_SRC_FIFO_OFLOW … #define FLD_FIELD … #define FLD_AFD_FMT_STAT … #define FLD_MV_TYPE2_PAIR … #define FLD_MV_T3CS … #define FLD_MV_CS … #define FLD_MV_PSP … /* Reserved [3] */ #define FLD_MV_CDAT … /*****************************************************************************/ #define INT_STAT_MASK … #define FLD_COMB_3D_FIFO_MSK … #define FLD_WSS_DAT_AVAIL_MSK … #define FLD_GS2_DAT_AVAIL_MSK … #define FLD_GS1_DAT_AVAIL_MSK … #define FLD_CC_DAT_AVAIL_MSK … #define FLD_VPRES_CHANGE_MSK … #define FLD_MV_CHANGE_MSK … #define FLD_END_VBI_EVEN_MSK … #define FLD_END_VBI_ODD_MSK … #define FLD_FMT_CHANGE_MSK … #define FLD_VSYNC_TRAIL_MSK … #define FLD_HLOCK_CHANGE_MSK … #define FLD_VLOCK_CHANGE_MSK … #define FLD_CSC_LOCK_CHANGE_MSK … #define FLD_SRC_FIFO_UFLOW_MSK … #define FLD_SRC_FIFO_OFLOW_MSK … #define FLD_COMB_3D_FIFO_STAT … #define FLD_WSS_DAT_AVAIL_STAT … #define FLD_GS2_DAT_AVAIL_STAT … #define FLD_GS1_DAT_AVAIL_STAT … #define FLD_CC_DAT_AVAIL_STAT … #define FLD_VPRES_CHANGE_STAT … #define FLD_MV_CHANGE_STAT … #define FLD_END_VBI_EVEN_STAT … #define FLD_END_VBI_ODD_STAT … #define FLD_FMT_CHANGE_STAT … #define FLD_VSYNC_TRAIL_STAT … #define FLD_HLOCK_CHANGE_STAT … #define FLD_VLOCK_CHANGE_STAT … #define FLD_CSC_LOCK_CHANGE_STAT … #define FLD_SRC_FIFO_UFLOW_STAT … #define FLD_SRC_FIFO_OFLOW_STAT … /*****************************************************************************/ #define LUMA_CTRL … #define BRIGHTNESS_CTRL_BYTE … #define CONTRAST_CTRL_BYTE … #define LUMA_CTRL_BYTE_3 … #define FLD_LUMA_CORE_SEL … #define FLD_RANGE … /* Reserved [19] */ #define FLD_PEAK_EN … #define FLD_PEAK_SEL … #define FLD_CNTRST … #define FLD_BRITE … /*****************************************************************************/ #define HSCALE_CTRL … #define FLD_HFILT … #define FLD_HSCALE … /*****************************************************************************/ #define VSCALE_CTRL … #define FLD_LINE_AVG_DIS … /* Reserved [23:20] */ #define FLD_VS_INTRLACE … #define FLD_VFILT … /* Reserved [15:13] */ #define FLD_VSCALE … /*****************************************************************************/ #define CHROMA_CTRL … #define USAT_CTRL_BYTE … #define VSAT_CTRL_BYTE … #define HUE_CTRL_BYTE … #define FLD_C_LPF_EN … #define FLD_CHR_DELAY … #define FLD_C_CORE_SEL … #define FLD_HUE … #define FLD_VSAT … #define FLD_USAT … /*****************************************************************************/ #define VBI_LINE_CTRL1 … #define FLD_VBI_MD_LINE4 … #define FLD_VBI_MD_LINE3 … #define FLD_VBI_MD_LINE2 … #define FLD_VBI_MD_LINE1 … /*****************************************************************************/ #define VBI_LINE_CTRL2 … #define FLD_VBI_MD_LINE8 … #define FLD_VBI_MD_LINE7 … #define FLD_VBI_MD_LINE6 … #define FLD_VBI_MD_LINE5 … /*****************************************************************************/ #define VBI_LINE_CTRL3 … #define FLD_VBI_MD_LINE12 … #define FLD_VBI_MD_LINE11 … #define FLD_VBI_MD_LINE10 … #define FLD_VBI_MD_LINE9 … /*****************************************************************************/ #define VBI_LINE_CTRL4 … #define FLD_VBI_MD_LINE16 … #define FLD_VBI_MD_LINE15 … #define FLD_VBI_MD_LINE14 … #define FLD_VBI_MD_LINE13 … /*****************************************************************************/ #define VBI_LINE_CTRL5 … #define FLD_VBI_MD_LINE17 … /*****************************************************************************/ #define VBI_FC_CFG … #define FLD_FC_ALT2 … #define FLD_FC_ALT1 … #define FLD_FC_ALT2_TYPE … #define FLD_FC_ALT1_TYPE … /* Reserved [7:1] */ #define FLD_FC_SEARCH_MODE … /*****************************************************************************/ #define VBI_MISC_CFG1 … #define FLD_TTX_PKTADRU … #define FLD_TTX_PKTADRL … /* Reserved [7:6] */ #define FLD_MOJI_PACK_DIS … #define FLD_VPS_DEC_DIS … #define FLD_CRI_MARG_SCALE … #define FLD_EDGE_RESYNC_EN … #define FLD_ADAPT_SLICE_DIS … /*****************************************************************************/ #define VBI_MISC_CFG2 … #define FLD_HAMMING_TYPE … /* Reserved [23:20] */ #define FLD_WSS_FIFO_RST … #define FLD_GS2_FIFO_RST … #define FLD_GS1_FIFO_RST … #define FLD_CC_FIFO_RST … /* Reserved [15:12] */ #define FLD_VBI3_SDID … #define FLD_VBI2_SDID … #define FLD_VBI1_SDID … /*****************************************************************************/ #define VBI_PAY1 … #define FLD_GS1_FIFO_DAT … #define FLD_GS1_STAT … #define FLD_CC_FIFO_DAT … #define FLD_CC_STAT … /*****************************************************************************/ #define VBI_PAY2 … #define FLD_WSS_FIFO_DAT … #define FLD_WSS_STAT … #define FLD_GS2_FIFO_DAT … #define FLD_GS2_STAT … /*****************************************************************************/ #define VBI_CUST1_CFG1 … /* Reserved [31] */ #define FLD_VBI1_CRIWIN … #define FLD_VBI1_SLICE_DIST … #define FLD_VBI1_BITINC … #define FLD_VBI1_HDELAY … /*****************************************************************************/ #define VBI_CUST1_CFG2 … #define FLD_VBI1_FC_LENGTH … #define FLD_VBI1_FRAME_CODE … /*****************************************************************************/ #define VBI_CUST1_CFG3 … #define FLD_VBI1_HAM_EN … #define FLD_VBI1_FIFO_MODE … #define FLD_VBI1_FORMAT_TYPE … #define FLD_VBI1_PAYLD_LENGTH … #define FLD_VBI1_CRI_LENGTH … #define FLD_VBI1_CRI_MARGIN … #define FLD_VBI1_CRI_TIME … /*****************************************************************************/ #define VBI_CUST2_CFG1 … /* Reserved [31] */ #define FLD_VBI2_CRIWIN … #define FLD_VBI2_SLICE_DIST … #define FLD_VBI2_BITINC … #define FLD_VBI2_HDELAY … /*****************************************************************************/ #define VBI_CUST2_CFG2 … #define FLD_VBI2_FC_LENGTH … #define FLD_VBI2_FRAME_CODE … /*****************************************************************************/ #define VBI_CUST2_CFG3 … #define FLD_VBI2_HAM_EN … #define FLD_VBI2_FIFO_MODE … #define FLD_VBI2_FORMAT_TYPE … #define FLD_VBI2_PAYLD_LENGTH … #define FLD_VBI2_CRI_LENGTH … #define FLD_VBI2_CRI_MARGIN … #define FLD_VBI2_CRI_TIME … /*****************************************************************************/ #define VBI_CUST3_CFG1 … /* Reserved [31] */ #define FLD_VBI3_CRIWIN … #define FLD_VBI3_SLICE_DIST … #define FLD_VBI3_BITINC … #define FLD_VBI3_HDELAY … /*****************************************************************************/ #define VBI_CUST3_CFG2 … #define FLD_VBI3_FC_LENGTH … #define FLD_VBI3_FRAME_CODE … /*****************************************************************************/ #define VBI_CUST3_CFG3 … #define FLD_VBI3_HAM_EN … #define FLD_VBI3_FIFO_MODE … #define FLD_VBI3_FORMAT_TYPE … #define FLD_VBI3_PAYLD_LENGTH … #define FLD_VBI3_CRI_LENGTH … #define FLD_VBI3_CRI_MARGIN … #define FLD_VBI3_CRI_TIME … /*****************************************************************************/ #define HORIZ_TIM_CTRL … #define FLD_BGDEL_CNT … /* Reserved [23:22] */ #define FLD_HACTIVE_CNT … /* Reserved [11:10] */ #define FLD_HBLANK_CNT … /*****************************************************************************/ #define VERT_TIM_CTRL … #define FLD_V656BLANK_CNT … /* Reserved [23:22] */ #define FLD_VACTIVE_CNT … /* Reserved [11:10] */ #define FLD_VBLANK_CNT … /*****************************************************************************/ #define SRC_COMB_CFG … #define FLD_CCOMB_2LN_CHECK … #define FLD_CCOMB_3LN_EN … #define FLD_CCOMB_2LN_EN … #define FLD_CCOMB_3D_EN … /* Reserved [27] */ #define FLD_LCOMB_3LN_EN … #define FLD_LCOMB_2LN_EN … #define FLD_LCOMB_3D_EN … #define FLD_LUMA_LPF_SEL … #define FLD_UV_LPF_SEL … #define FLD_BLEND_SLOPE … #define FLD_CCOMB_REDUCE_EN … /* Reserved [14:10] */ #define FLD_SRC_DECIM_RATIO … /*****************************************************************************/ #define CHROMA_VBIOFF_CFG … #define FLD_VBI_VOFFSET … /* Reserved [23:20] */ #define FLD_SC_STEP … /*****************************************************************************/ #define FIELD_COUNT … #define FLD_FIELD_COUNT_FLD … /*****************************************************************************/ #define MISC_TIM_CTRL … #define FLD_DEBOUNCE_COUNT … #define FLD_VT_LINE_CNT_HYST … /* Reserved [27] */ #define FLD_AFD_STAT … #define FLD_VPRES_VERT_EN … /* Reserved [14:12] */ #define FLD_HR32 … #define FLD_TDALGN … #define FLD_TDFIELD … /* Reserved [8:6] */ #define FLD_TEMPDEC … /*****************************************************************************/ #define DFE_CTRL1 … #define FLD_CLAMP_AUTO_EN … #define FLD_AGC_AUTO_EN … #define FLD_VGA_CRUSH_EN … #define FLD_VGA_AUTO_EN … #define FLD_VBI_GATE_EN … #define FLD_CLAMP_LEVEL … /* Reserved [23:22] */ #define FLD_CLAMP_SKIP_CNT … #define FLD_AGC_GAIN … /* Reserved [7:6] */ #define FLD_VGA_GAIN … /*****************************************************************************/ #define DFE_CTRL2 … #define FLD_VGA_ACQUIRE_RANGE … #define FLD_VGA_TRACK_RANGE … #define FLD_VGA_SYNC … /*****************************************************************************/ #define DFE_CTRL3 … #define FLD_BP_PERCENT … #define FLD_DFT_THRESHOLD … /* Reserved [15:12] */ #define FLD_SYNC_WIDTH_SEL … #define FLD_BP_LOOP_GAIN … #define FLD_SYNC_LOOP_GAIN … /* Reserved [5:4] */ #define FLD_AGC_LOOP_GAIN … #define FLD_DCC_LOOP_GAIN … /*****************************************************************************/ #define PLL_CTRL … #define FLD_PLL_KD … #define FLD_PLL_KI … #define FLD_PLL_MAX_OFFSET … /*****************************************************************************/ #define HTL_CTRL … /* Reserved [31:24] */ #define FLD_AUTO_LOCK_SPD … #define FLD_MAN_FAST_LOCK … #define FLD_HTL_15K_EN … #define FLD_HTL_500K_EN … #define FLD_HTL_KD … #define FLD_HTL_KI … /*****************************************************************************/ #define COMB_CTRL … #define FLD_COMB_PHASE_LIMIT … #define FLD_CCOMB_ERR_LIMIT … #define FLD_LUMA_THRESHOLD … #define FLD_LCOMB_ERR_LIMIT … /*****************************************************************************/ #define CRUSH_CTRL … #define FLD_WTW_EN … #define FLD_CRUSH_FREQ … #define FLD_MAJ_SEL_EN … #define FLD_MAJ_SEL … /* Reserved [17:15] */ #define FLD_SYNC_TIP_REDUCE … /* Reserved [8:6] */ #define FLD_SYNC_TIP_INC … /*****************************************************************************/ #define SOFT_RST_CTRL … #define FLD_VD_SOFT_RST … /* Reserved [14:12] */ #define FLD_REG_RST_MSK … #define FLD_VOF_RST_MSK … #define FLD_MVDET_RST_MSK … #define FLD_VBI_RST_MSK … #define FLD_SCALE_RST_MSK … #define FLD_CHROMA_RST_MSK … #define FLD_LUMA_RST_MSK … #define FLD_VTG_RST_MSK … #define FLD_YCSEP_RST_MSK … #define FLD_SRC_RST_MSK … #define FLD_DFE_RST_MSK … /* Reserved [0] */ /*****************************************************************************/ #define MV_DT_CTRL1 … /* Reserved [31:29] */ #define FLD_PSP_STOP_LINE … /* Reserved [23:21] */ #define FLD_PSP_STRT_LINE … /* Reserved [15] */ #define FLD_PSP_LLIMW … /* Reserved [7] */ #define FLD_PSP_ULIMW … /*****************************************************************************/ #define MV_DT_CTRL2 … #define FLD_CS_STOPWIN … #define FLD_CS_STRTWIN … #define FLD_CS_WIDTH … #define FLD_PSP_SPEC_VAL … /*****************************************************************************/ #define MV_DT_CTRL3 … #define FLD_AUTO_RATE_DIS … #define FLD_HLOCK_DIS … #define FLD_SEL_FIELD_CNT … #define FLD_CS_TYPE2_SEL … #define FLD_CS_LINE_THRSH_SEL … #define FLD_CS_ATHRESH_SEL … #define FLD_PSP_SPEC_SEL … #define FLD_PSP_LINES_SEL … #define FLD_FIELD_CNT … #define FLD_CS_TYPE2_CNT … #define FLD_CS_LINE_CNT … #define FLD_CS_ATHRESH_LEV … /*****************************************************************************/ #define CHIP_VERSION … /* Cx231xx redefine */ #define VERSION … #define FLD_REV_ID … /*****************************************************************************/ #define MISC_DIAG_CTRL … /* Reserved [31:24] */ #define FLD_SC_CONVERGE_THRESH … #define FLD_CCOMB_ERR_LIMIT_3D … #define FLD_LCOMB_ERR_LIMIT_3D … /*****************************************************************************/ #define VBI_PASS_CTRL … #define FLD_VBI_PASS_MD … #define FLD_VBI_SETUP_DIS … #define FLD_PASS_LINE_CTRL … /*****************************************************************************/ /* Cx231xx redefine */ #define VCR_DET_CTRL … #define FLD_EN_FIELD_PHASE_DET … #define FLD_EN_HEAD_SW_DET … #define FLD_FIELD_PHASE_LENGTH … /* Reserved [29:25] */ #define FLD_FIELD_PHASE_DELAY … #define FLD_FIELD_PHASE_LIMIT … #define FLD_HEAD_SW_DET_LIMIT … /*****************************************************************************/ #define DL_CTL … #define DL_CTL_ADDRESS_LOW … #define DL_CTL_ADDRESS_HIGH … #define DL_CTL_DATA … #define DL_CTL_CONTROL … /* Reserved [31:5] */ #define FLD_START_8051 … #define FLD_DL_ENABLE … #define FLD_DL_AUTO_INC … #define FLD_DL_MAP … /*****************************************************************************/ #define STD_DET_STATUS … #define FLD_SPARE_STATUS1 … #define FLD_SPARE_STATUS0 … #define FLD_MOD_DET_STATUS1 … #define FLD_MOD_DET_STATUS0 … /*****************************************************************************/ #define AUD_BUILD_NUM … #define AUD_VER_NUM … #define STD_DET_CTL … #define STD_DET_CTL_AUD_CTL … #define STD_DET_CTL_PREF_MODE … #define FLD_SPARE_CTL0 … #define FLD_DIS_DBX … #define FLD_DIS_BTSC … #define FLD_DIS_NICAM_A2 … #define FLD_VIDEO_PRESENT … #define FLD_DW8051_VIDEO_FORMAT … #define FLD_PREF_DEC_MODE … #define FLD_AUD_CONFIG … /*****************************************************************************/ #define DW8051_INT … #define FLD_VIDEO_PRESENT_CHANGE … #define FLD_VIDEO_CHANGE … #define FLD_RDS_READY … #define FLD_AC97_INT … #define FLD_NICAM_BIT_ERROR_TOO_HIGH … #define FLD_NICAM_LOCK … #define FLD_NICAM_UNLOCK … #define FLD_DFT4_TH_CMP … /* Reserved [23:22] */ #define FLD_LOCK_IND_INT … #define FLD_DFT3_TH_CMP … #define FLD_DFT2_TH_CMP … #define FLD_DFT1_TH_CMP … #define FLD_FM2_DFT_TH_CMP … #define FLD_FM1_DFT_TH_CMP … #define FLD_VIDEO_PRESENT_EN … #define FLD_VIDEO_CHANGE_EN … #define FLD_RDS_READY_EN … #define FLD_AC97_INT_EN … #define FLD_NICAM_BIT_ERROR_TOO_HIGH_EN … #define FLD_NICAM_LOCK_EN … #define FLD_NICAM_UNLOCK_EN … #define FLD_DFT4_TH_CMP_EN … /* Reserved [7] */ #define FLD_DW8051_INT6_CTL1 … #define FLD_DW8051_INT5_CTL1 … #define FLD_DW8051_INT4_CTL1 … #define FLD_DW8051_INT3_CTL1 … #define FLD_DW8051_INT2_CTL1 … #define FLD_DW8051_INT1_CTL1 … #define FLD_DW8051_INT0_CTL1 … /*****************************************************************************/ #define GENERAL_CTL … #define FLD_RDS_INT … #define FLD_NBER_INT … #define FLD_NLL_INT … #define FLD_IFL_INT … #define FLD_FDL_INT … #define FLD_AFC_INT … #define FLD_AMC_INT … #define FLD_AC97_INT_CTL … #define FLD_RDS_INT_DIS … #define FLD_NBER_INT_DIS … #define FLD_NLL_INT_DIS … #define FLD_IFL_INT_DIS … #define FLD_FDL_INT_DIS … #define FLD_FC_INT_DIS … #define FLD_AMC_INT_DIS … #define FLD_AC97_INT_DIS … #define FLD_REV_NUM … /* Reserved [7:5] */ #define FLD_DBX_SOFT_RESET_REG … #define FLD_AD_SOFT_RESET_REG … #define FLD_SRC_SOFT_RESET_REG … #define FLD_CDMOD_SOFT_RESET … #define FLD_8051_SOFT_RESET … /*****************************************************************************/ #define AAGC_CTL … #define FLD_AFE_12DB_EN … #define FLD_AAGC_DEFAULT_EN … #define FLD_AAGC_DEFAULT … /* Reserved [23] */ #define FLD_AAGC_GAIN … #define FLD_AAGC_TH … /* Reserved [15:14] */ #define FLD_AAGC_HYST2 … /* Reserved [7:6] */ #define FLD_AAGC_HYST1 … /*****************************************************************************/ #define IF_SRC_CTL … #define FLD_DBX_BYPASS … /* Reserved [30:25] */ #define FLD_IF_SRC_MODE … /* Reserved [23:18] */ #define FLD_IF_SRC_PHASE_INC … /*****************************************************************************/ #define ANALOG_DEMOD_CTL … #define FLD_ROT1_PHACC_PROG … /* Reserved [15] */ #define FLD_FM1_DELAY_FIX … #define FLD_PDF4_SHIFT … #define FLD_PDF3_SHIFT … #define FLD_PDF2_SHIFT … #define FLD_PDF1_SHIFT … #define FLD_FMBYPASS_MODE2 … #define FLD_FMBYPASS_MODE1 … #define FLD_NICAM_MODE … #define FLD_BTSC_FMRADIO_MODE … /*****************************************************************************/ #define ROT_FREQ_CTL … #define FLD_ROT3_PHACC_PROG … #define FLD_ROT2_PHACC_PROG … /*****************************************************************************/ #define FM_CTL … #define FLD_FM2_DC_FB_SHIFT … #define FLD_FM2_DC_INT_SHIFT … #define FLD_FM2_AFC_RESET … #define FLD_FM2_DC_PASS_IN … #define FLD_FM2_DAGC_SHIFT … #define FLD_FM2_CORDIC_SHIFT … #define FLD_FM1_DC_FB_SHIFT … #define FLD_FM1_DC_INT_SHIFT … #define FLD_FM1_AFC_RESET … #define FLD_FM1_DC_PASS_IN … #define FLD_FM1_DAGC_SHIFT … #define FLD_FM1_CORDIC_SHIFT … /*****************************************************************************/ #define LPF_PDF_CTL … /* Reserved [31:30] */ #define FLD_LPF32_SHIFT1 … #define FLD_LPF32_SHIFT2 … #define FLD_LPF160_SHIFTA … #define FLD_LPF160_SHIFTB … #define FLD_LPF160_SHIFTC … #define FLD_LPF32_COEF_SEL2 … #define FLD_LPF32_COEF_SEL1 … #define FLD_LPF160_COEF_SELC … #define FLD_LPF160_COEF_SELB … #define FLD_LPF160_COEF_SELA … #define FLD_LPF160_IN_EN_REG … #define FLD_PDF4_PDF_SEL … #define FLD_PDF3_PDF_SEL … #define FLD_PDF2_PDF_SEL … #define FLD_PDF1_PDF_SEL … /*****************************************************************************/ #define DFT1_CTL1 … #define FLD_DFT1_DWELL … #define FLD_DFT1_FREQ … /*****************************************************************************/ #define DFT1_CTL2 … #define FLD_DFT1_THRESHOLD … #define FLD_DFT1_CMP_CTL … #define FLD_DFT1_AVG … /* Reserved [3:1] */ #define FLD_DFT1_START … /*****************************************************************************/ #define DFT1_STATUS … #define FLD_DFT1_DONE … #define FLD_DFT1_TH_CMP_STAT … #define FLD_DFT1_RESULT … /*****************************************************************************/ #define DFT2_CTL1 … #define FLD_DFT2_DWELL … #define FLD_DFT2_FREQ … /*****************************************************************************/ #define DFT2_CTL2 … #define FLD_DFT2_THRESHOLD … #define FLD_DFT2_CMP_CTL … #define FLD_DFT2_AVG … /* Reserved [3:1] */ #define FLD_DFT2_START … /*****************************************************************************/ #define DFT2_STATUS … #define FLD_DFT2_DONE … #define FLD_DFT2_TH_CMP_STAT … #define FLD_DFT2_RESULT … /*****************************************************************************/ #define DFT3_CTL1 … #define FLD_DFT3_DWELL … #define FLD_DFT3_FREQ … /*****************************************************************************/ #define DFT3_CTL2 … #define FLD_DFT3_THRESHOLD … #define FLD_DFT3_CMP_CTL … #define FLD_DFT3_AVG … /* Reserved [3:1] */ #define FLD_DFT3_START … /*****************************************************************************/ #define DFT3_STATUS … #define FLD_DFT3_DONE … #define FLD_DFT3_TH_CMP_STAT … #define FLD_DFT3_RESULT … /*****************************************************************************/ #define DFT4_CTL1 … #define FLD_DFT4_DWELL … #define FLD_DFT4_FREQ … /*****************************************************************************/ #define DFT4_CTL2 … #define FLD_DFT4_THRESHOLD … #define FLD_DFT4_CMP_CTL … #define FLD_DFT4_AVG … /* Reserved [3:1] */ #define FLD_DFT4_START … /*****************************************************************************/ #define DFT4_STATUS … #define FLD_DFT4_DONE … #define FLD_DFT4_TH_CMP_STAT … #define FLD_DFT4_RESULT … /*****************************************************************************/ #define AM_MTS_DET … #define FLD_AM_MTS_MODE … /* Reserved [30:26] */ #define FLD_AM_SUB … #define FLD_AM_GAIN_EN … /* Reserved [23:16] */ #define FLD_AMMTS_GAIN_SCALE … #define FLD_MTS_PDF_SHIFT … #define FLD_AM_REG_GAIN … #define FLD_AGC_REF … /*****************************************************************************/ #define ANALOG_MUX_CTL … /* Reserved [31:29] */ #define FLD_MUX21_SEL … #define FLD_MUX20_SEL … #define FLD_MUX19_SEL … #define FLD_MUX18_SEL … #define FLD_MUX17_SEL … #define FLD_MUX16_SEL … #define FLD_MUX15_SEL … #define FLD_MUX14_SEL … #define FLD_MUX13_SEL … #define FLD_MUX12_SEL … #define FLD_MUX11_SEL … #define FLD_MUX10_SEL … #define FLD_MUX9_SEL … #define FLD_MUX8_SEL … #define FLD_MUX7_SEL … #define FLD_MUX6_SEL … #define FLD_MUX5_SEL … #define FLD_MUX4_SEL … #define FLD_MUX3_SEL … #define FLD_MUX2_SEL … #define FLD_MUX1_SEL … /*****************************************************************************/ /* Cx231xx redefine */ #define DPLL_CTRL1 … #define DIG_PLL_CTL1 … #define FLD_PLL_STATUS … #define FLD_BANDWIDTH_SELECT … #define FLD_PLL_SHIFT_REG … #define FLD_PHASE_SHIFT … /*****************************************************************************/ /* Cx231xx redefine */ #define DPLL_CTRL2 … #define DIG_PLL_CTL2 … #define FLD_PLL_UNLOCK_THR … #define FLD_PLL_LOCK_THR … /* Reserved [15:8] */ #define FLD_AM_PDF_SEL2 … #define FLD_AM_PDF_SEL1 … #define FLD_DPLL_FSM_CTRL … /* Reserved [1] */ #define FLD_PLL_PILOT_DET … /*****************************************************************************/ /* Cx231xx redefine */ #define DPLL_CTRL3 … #define DIG_PLL_CTL3 … #define FLD_DISABLE_LOOP … #define FLD_A1_DS1_SEL … #define FLD_A1_DS2_SEL … #define FLD_A1_KI … #define FLD_A1_KD … /*****************************************************************************/ /* Cx231xx redefine */ #define DPLL_CTRL4 … #define DIG_PLL_CTL4 … #define FLD_A2_DS1_SEL … #define FLD_A2_DS2_SEL … #define FLD_A2_KI … #define FLD_A2_KD … /*****************************************************************************/ /* Cx231xx redefine */ #define DPLL_CTRL5 … #define DIG_PLL_CTL5 … #define FLD_TRK_DS1_SEL … #define FLD_TRK_DS2_SEL … #define FLD_TRK_KI … #define FLD_TRK_KD … /*****************************************************************************/ #define DEEMPH_GAIN_CTL … #define FLD_DEEMPH2_GAIN … #define FLD_DEEMPH1_GAIN … /*****************************************************************************/ /* Cx231xx redefine */ #define DEEMPH_COEFF1 … #define DEEMPH_COEF1 … #define FLD_DEEMPH_B0 … #define FLD_DEEMPH_A0 … /*****************************************************************************/ /* Cx231xx redefine */ #define DEEMPH_COEFF2 … #define DEEMPH_COEF2 … #define FLD_DEEMPH_B1 … #define FLD_DEEMPH_A1 … /*****************************************************************************/ #define DBX1_CTL1 … #define FLD_DBX1_WBE_GAIN … #define FLD_DBX1_IN_GAIN … /*****************************************************************************/ #define DBX1_CTL2 … #define FLD_DBX1_SE_BYPASS … #define FLD_DBX1_SE_GAIN … /*****************************************************************************/ #define DBX1_RMS_SE … #define FLD_DBX1_RMS_WBE … #define FLD_DBX1_RMS_SE_FLD … /*****************************************************************************/ #define DBX2_CTL1 … #define FLD_DBX2_WBE_GAIN … #define FLD_DBX2_IN_GAIN … /*****************************************************************************/ #define DBX2_CTL2 … #define FLD_DBX2_SE_BYPASS … #define FLD_DBX2_SE_GAIN … /*****************************************************************************/ #define DBX2_RMS_SE … #define FLD_DBX2_RMS_WBE … #define FLD_DBX2_RMS_SE_FLD … /*****************************************************************************/ #define AM_FM_DIFF … /* Reserved [31] */ #define FLD_FM_DIFF_OUT … /* Reserved [15] */ #define FLD_AM_DIFF_OUT … /*****************************************************************************/ #define NICAM_FAW … #define FLD_FAWDETWINEND … #define FLD_FAWDETWINSTR … /* Reserved [15:12] */ #define FLD_FAWDETTHRSHLD3 … #define FLD_FAWDETTHRSHLD2 … #define FLD_FAWDETTHRSHLD1 … /*****************************************************************************/ /* Cx231xx redefine */ #define DEEMPH_GAIN … #define NICAM_DEEMPHGAIN … /* Reserved [31:18] */ #define FLD_DEEMPHGAIN … /*****************************************************************************/ /* Cx231xx redefine */ #define DEEMPH_NUMER1 … #define NICAM_DEEMPHNUMER1 … /* Reserved [31:18] */ #define FLD_DEEMPHNUMER1 … /*****************************************************************************/ /* Cx231xx redefine */ #define DEEMPH_NUMER2 … #define NICAM_DEEMPHNUMER2 … /* Reserved [31:18] */ #define FLD_DEEMPHNUMER2 … /*****************************************************************************/ /* Cx231xx redefine */ #define DEEMPH_DENOM1 … #define NICAM_DEEMPHDENOM1 … /* Reserved [31:18] */ #define FLD_DEEMPHDENOM1 … /*****************************************************************************/ /* Cx231xx redefine */ #define DEEMPH_DENOM2 … #define NICAM_DEEMPHDENOM2 … /* Reserved [31:18] */ #define FLD_DEEMPHDENOM2 … /*****************************************************************************/ #define NICAM_ERRLOG_CTL1 … /* Reserved [31:28] */ #define FLD_ERRINTRPTTHSHLD1 … /* Reserved [15:12] */ #define FLD_ERRLOGPERIOD … /*****************************************************************************/ #define NICAM_ERRLOG_CTL2 … /* Reserved [31:28] */ #define FLD_ERRINTRPTTHSHLD3 … /* Reserved [15:12] */ #define FLD_ERRINTRPTTHSHLD2 … /*****************************************************************************/ #define NICAM_ERRLOG_STS1 … /* Reserved [31:28] */ #define FLD_ERRLOG2 … /* Reserved [15:12] */ #define FLD_ERRLOG1 … /*****************************************************************************/ #define NICAM_ERRLOG_STS2 … /* Reserved [31:12] */ #define FLD_ERRLOG3 … /*****************************************************************************/ #define NICAM_STATUS … /* Reserved [31:20] */ #define FLD_NICAM_CIB … #define FLD_NICAM_LOCK_STAT … #define FLD_NICAM_MUTE … #define FLD_NICAMADDIT_DATA … #define FLD_NICAMCNTRL … /*****************************************************************************/ #define DEMATRIX_CTL … #define FLD_AC97_IN_SHIFT … #define FLD_I2S_IN_SHIFT … #define FLD_DEMATRIX_SEL_CTL … /* Reserved [15:11] */ #define FLD_DMTRX_BYPASS … #define FLD_DEMATRIX_MODE … /* Reserved [7:6] */ #define FLD_PH_DBX_SEL … #define FLD_PH_CH_SEL … #define FLD_PHASE_FIX … /*****************************************************************************/ #define PATH1_CTL1 … /* Reserved [31:29] */ #define FLD_PATH1_MUTE_CTL … /* Reserved [23:22] */ #define FLD_PATH1_AVC_CG … #define FLD_PATH1_AVC_RT … #define FLD_PATH1_AVC_AT … #define FLD_PATH1_AVC_STEREO … #define FLD_PATH1_AVC_CR … #define FLD_PATH1_AVC_RMS_CON … #define FLD_PATH1_SEL_CTL … /*****************************************************************************/ #define PATH1_VOL_CTL … #define FLD_PATH1_AVC_THRESHOLD … #define FLD_PATH1_BAL_LEFT … #define FLD_PATH1_BAL_LEVEL … #define FLD_PATH1_VOLUME … /*****************************************************************************/ #define PATH1_EQ_CTL … /* Reserved [31:30] */ #define FLD_PATH1_EQ_TREBLE_VOL … /* Reserved [23:22] */ #define FLD_PATH1_EQ_MID_VOL … /* Reserved [15:14] */ #define FLD_PATH1_EQ_BASS_VOL … /* Reserved [7:1] */ #define FLD_PATH1_EQ_BAND_SEL … /*****************************************************************************/ #define PATH1_SC_CTL … #define FLD_PATH1_SC_THRESHOLD … #define FLD_PATH1_SC_RT … #define FLD_PATH1_SC_AT … #define FLD_PATH1_SC_STEREO … #define FLD_PATH1_SC_CR … #define FLD_PATH1_SC_RMS_CON … /*****************************************************************************/ #define PATH2_CTL1 … /* Reserved [31:26] */ #define FLD_PATH2_MUTE_CTL … /* Reserved [23:22] */ #define FLD_PATH2_AVC_CG … #define FLD_PATH2_AVC_RT … #define FLD_PATH2_AVC_AT … #define FLD_PATH2_AVC_STEREO … #define FLD_PATH2_AVC_CR … #define FLD_PATH2_AVC_RMS_CON … #define FLD_PATH2_SEL_CTL … /*****************************************************************************/ #define PATH2_VOL_CTL … #define FLD_PATH2_AVC_THRESHOLD … #define FLD_PATH2_BAL_LEFT … #define FLD_PATH2_BAL_LEVEL … #define FLD_PATH2_VOLUME … /*****************************************************************************/ #define PATH2_EQ_CTL … /* Reserved [31:30] */ #define FLD_PATH2_EQ_TREBLE_VOL … /* Reserved [23:22] */ #define FLD_PATH2_EQ_MID_VOL … /* Reserved [15:14] */ #define FLD_PATH2_EQ_BASS_VOL … /* Reserved [7:1] */ #define FLD_PATH2_EQ_BAND_SEL … /*****************************************************************************/ #define PATH2_SC_CTL … #define FLD_PATH2_SC_THRESHOLD … #define FLD_PATH2_SC_RT … #define FLD_PATH2_SC_AT … #define FLD_PATH2_SC_STEREO … #define FLD_PATH2_SC_CR … #define FLD_PATH2_SC_RMS_CON … /*****************************************************************************/ #define SRC_CTL … #define FLD_SRC_STATUS … #define FLD_FIFO_LF_EN … #define FLD_BYPASS_LI … #define FLD_BYPASS_PF … /*****************************************************************************/ #define SRC_LF_COEF … #define FLD_LOOP_FILTER_COEF2 … #define FLD_LOOP_FILTER_COEF1 … /*****************************************************************************/ #define SRC1_CTL … /* Reserved [31:28] */ #define FLD_SRC1_FIFO_RD_TH … /* Reserved [23:18] */ #define FLD_SRC1_PHASE_INC … /*****************************************************************************/ #define SRC2_CTL … /* Reserved [31:28] */ #define FLD_SRC2_FIFO_RD_TH … /* Reserved [23:18] */ #define FLD_SRC2_PHASE_INC … /*****************************************************************************/ #define SRC3_CTL … /* Reserved [31:28] */ #define FLD_SRC3_FIFO_RD_TH … /* Reserved [23:18] */ #define FLD_SRC3_PHASE_INC … /*****************************************************************************/ #define SRC4_CTL … /* Reserved [31:28] */ #define FLD_SRC4_FIFO_RD_TH … /* Reserved [23:18] */ #define FLD_SRC4_PHASE_INC … /*****************************************************************************/ #define SRC5_CTL … /* Reserved [31:28] */ #define FLD_SRC5_FIFO_RD_TH … /* Reserved [23:18] */ #define FLD_SRC5_PHASE_INC … /*****************************************************************************/ #define SRC6_CTL … /* Reserved [31:28] */ #define FLD_SRC6_FIFO_RD_TH … /* Reserved [23:18] */ #define FLD_SRC6_PHASE_INC … /*****************************************************************************/ #define BAND_OUT_SEL … #define FLD_SRC6_IN_SEL … #define FLD_SRC6_CLK_SEL … #define FLD_SRC5_IN_SEL … #define FLD_SRC5_CLK_SEL … #define FLD_SRC4_IN_SEL … #define FLD_SRC4_CLK_SEL … #define FLD_SRC3_IN_SEL … #define FLD_SRC3_CLK_SEL … #define FLD_BASEBAND_BYPASS_CTL … #define FLD_AC97_SRC_SEL … #define FLD_I2S_SRC_SEL … #define FLD_PARALLEL2_SRC_SEL … #define FLD_PARALLEL1_SRC_SEL … /*****************************************************************************/ #define I2S_IN_CTL … /* Reserved [31:11] */ #define FLD_I2S_UP2X_BW20K … #define FLD_I2S_UP2X_BYPASS … #define FLD_I2S_IN_MASTER_MODE … #define FLD_I2S_IN_SONY_MODE … #define FLD_I2S_IN_RIGHT_JUST … #define FLD_I2S_IN_WS_SEL … #define FLD_I2S_IN_BCN_DEL … /*****************************************************************************/ #define I2S_OUT_CTL … /* Reserved [31:17] */ #define FLD_I2S_OUT_SOFT_RESET_EN … /* Reserved [15:9] */ #define FLD_I2S_OUT_MASTER_MODE … #define FLD_I2S_OUT_SONY_MODE … #define FLD_I2S_OUT_RIGHT_JUST … #define FLD_I2S_OUT_WS_SEL … #define FLD_I2S_OUT_BCN_DEL … /*****************************************************************************/ #define AC97_CTL … /* Reserved [31:26] */ #define FLD_AC97_UP2X_BW20K … #define FLD_AC97_UP2X_BYPASS … /* Reserved [23:17] */ #define FLD_AC97_RST_ACL … /* Reserved [15:9] */ #define FLD_AC97_WAKE_UP_SYNC … /* Reserved [7:1] */ #define FLD_AC97_SHUTDOWN … /* Cx231xx redefine */ #define QPSK_IAGC_CTL1 … #define QPSK_IAGC_CTL2 … #define QPSK_FEPR_FREQ … #define QPSK_BTL_CTL1 … #define QPSK_BTL_CTL2 … #define QPSK_CTL_CTL1 … #define QPSK_CTL_CTL2 … #define QPSK_MF_FAGC_CTL … #define QPSK_EQ_CTL … #define QPSK_LOCK_CTL … /*****************************************************************************/ #define FM1_DFT_CTL … #define FLD_FM1_DFT_THRESHOLD … /* Reserved [15:8] */ #define FLD_FM1_DFT_CMP_CTL … #define FLD_FM1_DFT_AVG … /* Reserved [3:1] */ #define FLD_FM1_DFT_START … /*****************************************************************************/ #define FM1_DFT_STATUS … #define FLD_FM1_DFT_DONE … /* Reserved [30:19] */ #define FLD_FM_DFT_TH_CMP … #define FLD_FM1_DFT … /*****************************************************************************/ #define FM2_DFT_CTL … #define FLD_FM2_DFT_THRESHOLD … /* Reserved [15:8] */ #define FLD_FM2_DFT_CMP_CTL … #define FLD_FM2_DFT_AVG … /* Reserved [3:1] */ #define FLD_FM2_DFT_START … /*****************************************************************************/ #define FM2_DFT_STATUS … #define FLD_FM2_DFT_DONE … /* Reserved [30:19] */ #define FLD_FM2_DFT_TH_CMP_STAT … #define FLD_FM2_DFT … /*****************************************************************************/ /* Cx231xx redefine */ #define AAGC_STATUS_REG … #define AAGC_STATUS … /* Reserved [31:27] */ #define FLD_FM2_DAGC_OUT … /* Reserved [23:19] */ #define FLD_FM1_DAGC_OUT … /* Reserved [15:6] */ #define FLD_AFE_VGA_OUT … /*****************************************************************************/ #define MTS_GAIN_STATUS … /* Reserved [31:14] */ #define FLD_MTS_GAIN … #define RDS_OUT … #define FLD_RDS_Q … #define FLD_RDS_I … /*****************************************************************************/ #define AUTOCONFIG_REG … /* Reserved [31:4] */ #define FLD_AUTOCONFIG_MODE … #define FM_AFC … #define FLD_FM2_AFC … #define FLD_FM1_AFC … /*****************************************************************************/ /* Cx231xx redefine */ #define NEW_SPARE … #define NEW_SPARE_REG … /*****************************************************************************/ #define DBX_ADJ … /* Reserved [31:28] */ #define FLD_DBX2_ADJ … /* Reserved [15:12] */ #define FLD_DBX1_ADJ … #define VID_FMT_AUTO … #define VID_FMT_NTSC_M … #define VID_FMT_NTSC_J … #define VID_FMT_NTSC_443 … #define VID_FMT_PAL_BDGHI … #define VID_FMT_PAL_M … #define VID_FMT_PAL_N … #define VID_FMT_PAL_NC … #define VID_FMT_PAL_60 … #define VID_FMT_SECAM … #define VID_FMT_SECAM_60 … #define INPUT_MODE_CVBS_0 … #define INPUT_MODE_YC_1 … #define INPUT_MODE_YC2_2 … #define INPUT_MODE_YUV_3 … #define LUMA_LPF_LOW_BANDPASS … #define LUMA_LPF_MEDIUM_BANDPASS … #define LUMA_LPF_HIGH_BANDPASS … #define UV_LPF_LOW_BANDPASS … #define UV_LPF_MEDIUM_BANDPASS … #define UV_LPF_HIGH_BANDPASS … #define TWO_TAP_FILT … #define THREE_TAP_FILT … #define FOUR_TAP_FILT … #define FIVE_TAP_FILT … #define AUD_CHAN_SRC_PARALLEL … #define AUD_CHAN_SRC_I2S_INPUT … #define AUD_CHAN_SRC_FLATIRON … #define AUD_CHAN_SRC_PARALLEL3 … #define OUT_MODE_601 … #define OUT_MODE_656 … #define OUT_MODE_VIP11 … #define OUT_MODE_VIP20 … #define PHASE_INC_49MHZ … #define PHASE_INC_56MHZ … #define PHASE_INC_28MHZ … #endif
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