/* SPDX-License-Identifier: GPL-2.0 */ /* * em28xx-reg.h - Register definitions for em28xx driver */ #define EM_GPIO_0 … #define EM_GPIO_1 … #define EM_GPIO_2 … #define EM_GPIO_3 … #define EM_GPIO_4 … #define EM_GPIO_5 … #define EM_GPIO_6 … #define EM_GPIO_7 … #define EM_GPO_0 … #define EM_GPO_1 … #define EM_GPO_2 … #define EM_GPO_3 … /* em28xx endpoints */ /* 0x82: (always ?) analog */ #define EM28XX_EP_AUDIO … /* 0x84: digital or analog */ /* em2800 registers */ #define EM2800_R08_AUDIOSRC … /* em28xx registers */ #define EM28XX_R00_CHIPCFG … /* em28xx Chip Configuration 0x00 */ #define EM2860_CHIPCFG_VENDOR_AUDIO … #define EM2860_CHIPCFG_I2S_VOLUME_CAPABLE … #define EM2820_CHIPCFG_I2S_3_SAMPRATES … #define EM2860_CHIPCFG_I2S_5_SAMPRATES … #define EM2820_CHIPCFG_I2S_1_SAMPRATE … #define EM2860_CHIPCFG_I2S_3_SAMPRATES … #define EM28XX_CHIPCFG_AC97 … #define EM28XX_CHIPCFG_AUDIOMASK … #define EM28XX_R01_CHIPCFG2 … /* em28xx Chip Configuration 2 0x01 */ #define EM28XX_CHIPCFG2_TS_PRESENT … #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_MASK … #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_1MF … #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_2MF … #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_4MF … #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_8MF … #define EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK … #define EM28XX_CHIPCFG2_TS_PACKETSIZE_188 … #define EM28XX_CHIPCFG2_TS_PACKETSIZE_376 … #define EM28XX_CHIPCFG2_TS_PACKETSIZE_564 … #define EM28XX_CHIPCFG2_TS_PACKETSIZE_752 … /* GPIO/GPO registers */ #define EM2880_R04_GPO … #define EM2820_R08_GPIO_CTRL … #define EM2820_R09_GPIO_STATE … #define EM28XX_R06_I2C_CLK … /* em28xx I2C Clock Register (0x06) */ #define EM28XX_I2C_CLK_ACK_LAST_READ … #define EM28XX_I2C_CLK_WAIT_ENABLE … #define EM28XX_I2C_EEPROM_ON_BOARD … #define EM28XX_I2C_EEPROM_KEY_VALID … #define EM2874_I2C_SECONDARY_BUS_SELECT … #define EM28XX_I2C_FREQ_1_5_MHZ … #define EM28XX_I2C_FREQ_25_KHZ … #define EM28XX_I2C_FREQ_400_KHZ … #define EM28XX_I2C_FREQ_100_KHZ … #define EM28XX_R0A_CHIPID … #define EM28XX_R0C_USBSUSP … #define EM28XX_R0C_USBSUSP_SNAPSHOT … #define EM28XX_R0E_AUDIOSRC … #define EM28XX_R0F_XCLK … /* em28xx XCLK Register (0x0f) */ #define EM28XX_XCLK_AUDIO_UNMUTE … #define EM28XX_XCLK_I2S_MSB_TIMING … #define EM28XX_XCLK_IR_RC5_MODE … #define EM28XX_XCLK_IR_NEC_CHK_PARITY … #define EM28XX_XCLK_FREQUENCY_30MHZ … #define EM28XX_XCLK_FREQUENCY_15MHZ … #define EM28XX_XCLK_FREQUENCY_10MHZ … #define EM28XX_XCLK_FREQUENCY_7_5MHZ … #define EM28XX_XCLK_FREQUENCY_6MHZ … #define EM28XX_XCLK_FREQUENCY_5MHZ … #define EM28XX_XCLK_FREQUENCY_4_3MHZ … #define EM28XX_XCLK_FREQUENCY_12MHZ … #define EM28XX_XCLK_FREQUENCY_20MHZ … #define EM28XX_XCLK_FREQUENCY_20MHZ_2 … #define EM28XX_XCLK_FREQUENCY_48MHZ … #define EM28XX_XCLK_FREQUENCY_24MHZ … #define EM28XX_R10_VINMODE … /* used by all non-camera devices: */ #define EM28XX_VINMODE_YUV422_CbYCrY … /* used by camera devices: */ #define EM28XX_VINMODE_YUV422_YUYV … #define EM28XX_VINMODE_YUV422_YVYU … #define EM28XX_VINMODE_YUV422_UYVY … #define EM28XX_VINMODE_YUV422_VYUY … #define EM28XX_VINMODE_RGB8_BGGR … #define EM28XX_VINMODE_RGB8_GRBG … #define EM28XX_VINMODE_RGB8_GBRG … #define EM28XX_VINMODE_RGB8_RGGB … /* * apparently: * bit 0: swap component 1+2 with 3+4 * => e.g.: YUYV => YVYU, BGGR => GRBG * bit 1: swap component 1 with 2 and 3 with 4 * => e.g.: YUYV => UYVY, BGGR => GBRG */ #define EM28XX_R11_VINCTRL … /* em28xx Video Input Control Register 0x11 */ #define EM28XX_VINCTRL_VBI_SLICED … #define EM28XX_VINCTRL_VBI_RAW … #define EM28XX_VINCTRL_VOUT_MODE_IN … #define EM28XX_VINCTRL_CCIR656_ENABLE … #define EM28XX_VINCTRL_VBI_16BIT_RAW … #define EM28XX_VINCTRL_FID_ON_HREF … #define EM28XX_VINCTRL_DUAL_EDGE_STROBE … #define EM28XX_VINCTRL_INTERLACED … #define EM28XX_R12_VINENABLE … #define EM28XX_R14_GAMMA … #define EM28XX_R15_RGAIN … #define EM28XX_R16_GGAIN … #define EM28XX_R17_BGAIN … #define EM28XX_R18_ROFFSET … #define EM28XX_R19_GOFFSET … #define EM28XX_R1A_BOFFSET … #define EM28XX_R1B_OFLOW … #define EM28XX_R1C_HSTART … #define EM28XX_R1D_VSTART … #define EM28XX_R1E_CWIDTH … #define EM28XX_R1F_CHEIGHT … #define EM28XX_R20_YGAIN … #define CONTRAST_DEFAULT … #define EM28XX_R21_YOFFSET … #define BRIGHTNESS_DEFAULT … #define EM28XX_R22_UVGAIN … #define SATURATION_DEFAULT … #define EM28XX_R23_UOFFSET … #define BLUE_BALANCE_DEFAULT … #define EM28XX_R24_VOFFSET … #define RED_BALANCE_DEFAULT … #define EM28XX_R25_SHARPNESS … #define SHARPNESS_DEFAULT … #define EM28XX_R26_COMPR … #define EM28XX_R27_OUTFMT … /* em28xx Output Format Register (0x27) */ #define EM28XX_OUTFMT_RGB_8_RGRG … #define EM28XX_OUTFMT_RGB_8_GRGR … #define EM28XX_OUTFMT_RGB_8_GBGB … #define EM28XX_OUTFMT_RGB_8_BGBG … #define EM28XX_OUTFMT_RGB_16_656 … #define EM28XX_OUTFMT_RGB_8_BAYER … #define EM28XX_OUTFMT_YUV211 … #define EM28XX_OUTFMT_YUV422_Y0UY1V … #define EM28XX_OUTFMT_YUV422_Y1UY0V … #define EM28XX_OUTFMT_YUV411 … #define EM28XX_R28_XMIN … #define EM28XX_R29_XMAX … #define EM28XX_R2A_YMIN … #define EM28XX_R2B_YMAX … #define EM28XX_R30_HSCALELOW … #define EM28XX_R31_HSCALEHIGH … #define EM28XX_R32_VSCALELOW … #define EM28XX_R33_VSCALEHIGH … #define EM28XX_HVSCALE_MAX … #define EM28XX_R34_VBI_START_H … #define EM28XX_R35_VBI_START_V … /* * NOTE: the EM276x (and EM25xx, EM277x/8x ?) (camera bridges) use these * registers for a different unknown purpose. * => register 0x34 is set to capture width / 16 * => register 0x35 is set to capture height / 16 */ #define EM28XX_R36_VBI_WIDTH … #define EM28XX_R37_VBI_HEIGHT … #define EM28XX_R40_AC97LSB … #define EM28XX_R41_AC97MSB … #define EM28XX_R42_AC97ADDR … #define EM28XX_R43_AC97BUSY … #define EM28XX_R45_IR … /* * 0x45 bit 7 - parity bit * bits 6-0 - count * 0x46 IR brand * 0x47 IR data */ /* em2874 registers */ #define EM2874_R50_IR_CONFIG … #define EM2874_R51_IR … #define EM2874_R5D_TS1_PKT_SIZE … #define EM2874_R5E_TS2_PKT_SIZE … /* * For both TS1 and TS2, In isochronous mode: * 0x01 188 bytes * 0x02 376 bytes * 0x03 564 bytes * 0x04 752 bytes * 0x05 940 bytes * In bulk mode: * 0x01..0xff total packet count in 188-byte */ #define EM2874_R5F_TS_ENABLE … /* em2874/174/84, em25xx, em276x/7x/8x GPIO registers */ /* * NOTE: not all ports are bonded out; * Some ports are multiplexed with special function I/O */ #define EM2874_R80_GPIO_P0_CTRL … #define EM2874_R81_GPIO_P1_CTRL … #define EM2874_R82_GPIO_P2_CTRL … #define EM2874_R83_GPIO_P3_CTRL … #define EM2874_R84_GPIO_P0_STATE … #define EM2874_R85_GPIO_P1_STATE … #define EM2874_R86_GPIO_P2_STATE … #define EM2874_R87_GPIO_P3_STATE … /* em2874 IR config register (0x50) */ #define EM2874_IR_NEC … #define EM2874_IR_NEC_NO_PARITY … #define EM2874_IR_RC5 … #define EM2874_IR_RC6_MODE_0 … #define EM2874_IR_RC6_MODE_6A … /* em2874 Transport Stream Enable Register (0x5f) */ #define EM2874_TS1_CAPTURE_ENABLE … #define EM2874_TS1_FILTER_ENABLE … #define EM2874_TS1_NULL_DISCARD … #define EM2874_TS2_CAPTURE_ENABLE … #define EM2874_TS2_FILTER_ENABLE … #define EM2874_TS2_NULL_DISCARD … /* register settings */ #define EM2800_AUDIO_SRC_TUNER … #define EM2800_AUDIO_SRC_LINE … #define EM28XX_AUDIO_SRC_TUNER … #define EM28XX_AUDIO_SRC_LINE … /* FIXME: Need to be populated with the other chip ID's */ enum em28xx_chip_id { … }; /* * Registers used by em202 */ /* EMP202 vendor registers */ #define EM202_EXT_MODEM_CTRL … #define EM202_GPIO_CONF … #define EM202_GPIO_POLARITY … #define EM202_GPIO_STICKY … #define EM202_GPIO_MASK … #define EM202_GPIO_STATUS … #define EM202_SPDIF_OUT_SEL … #define EM202_ANTIPOP … #define EM202_EAPD_GPIO_ACCESS …
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