/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * STK1160 driver * * Copyright (C) 2012 Ezequiel Garcia * <elezegarcia--a.t--gmail.com> * * Based on Easycap driver by R.M. Thomas * Copyright (C) 2010 R.M. Thomas * <rmthomas--a.t--sciolus.org> */ /* GPIO Control */ #define STK1160_GCTRL … /* Remote Wakeup Control */ #define STK1160_RMCTL … /* Power-on Strapping Data */ #define STK1160_POSVA … #define STK1160_POSV_L … #define STK1160_POSV_M … #define STK1160_POSV_H … #define STK1160_POSV_L_ACDOUT … #define STK1160_POSV_L_ACSYNC … /* * Decoder Control Register: * This byte controls capture start/stop * with bit #7 (0x?? OR 0x80 to activate). */ #define STK1160_DCTRL … /* * Decimation Control Register: * Byte 104: Horizontal Decimation Line Unit Count * Byte 105: Vertical Decimation Line Unit Count * Byte 106: Decimation Control * Bit 0 - Horizontal Decimation Control * 0 Horizontal decimation is disabled. * 1 Horizontal decimation is enabled. * Bit 1 - Decimates Half or More Column * 0 Decimates less than half from original column, * send count unit (0x105) before each unit skipped. * 1 Decimates half or more from original column, * skip count unit (0x105) before each unit sent. * Bit 2 - Vertical Decimation Control * 0 Vertical decimation is disabled. * 1 Vertical decimation is enabled. * Bit 3 - Vertical Greater or Equal to Half * 0 Decimates less than half from original row, * send count unit (0x105) before each unit skipped. * 1 Decimates half or more from original row, * skip count unit (0x105) before each unit sent. * Bit 4 - Decimation Unit * 0 Decimation will work with 2 rows or columns per unit. * 1 Decimation will work with 4 rows or columns per unit. */ #define STK1160_DMCTRL_H_UNITS … #define STK1160_DMCTRL_V_UNITS … #define STK1160_DMCTRL … #define STK1160_H_DEC_EN … #define STK1160_H_DEC_MODE … #define STK1160_V_DEC_EN … #define STK1160_V_DEC_MODE … #define STK1160_DEC_UNIT_SIZE … /* Capture Frame Start Position */ #define STK116_CFSPO … #define STK116_CFSPO_STX_L … #define STK116_CFSPO_STX_H … #define STK116_CFSPO_STY_L … #define STK116_CFSPO_STY_H … /* Capture Frame End Position */ #define STK116_CFEPO … #define STK116_CFEPO_ENX_L … #define STK116_CFEPO_ENX_H … #define STK116_CFEPO_ENY_L … #define STK116_CFEPO_ENY_H … /* Serial Interface Control */ #define STK1160_SICTL … #define STK1160_SICTL_CD … #define STK1160_SICTL_SDA … /* Serial Bus Write */ #define STK1160_SBUSW … #define STK1160_SBUSW_WA … #define STK1160_SBUSW_WD … /* Serial Bus Read */ #define STK1160_SBUSR … #define STK1160_SBUSR_RA … #define STK1160_SBUSR_RD … /* Alternate Serial Interface Control */ #define STK1160_ASIC … /* PLL Select Options */ #define STK1160_PLLSO … /* PLL Frequency Divider */ #define STK1160_PLLFD … /* Timing Generator */ #define STK1160_TIGEN … /* Timing Control Parameter */ #define STK1160_TICTL … /* AC97 Audio Control */ #define STK1160_AC97CTL_0 … #define STK1160_AC97CTL_1 … #define STK1160_AC97CTL_0_CR … #define STK1160_AC97CTL_0_CW … /* Use [0:6] bits of register 0x504 to set codec command address */ #define STK1160_AC97_ADDR … /* Use [16:31] bits of register 0x500 to set codec command data */ #define STK1160_AC97_CMD … /* Audio I2S Interface */ #define STK1160_I2SCTL … /* EEPROM Interface */ #define STK1160_EEPROM_SZ …
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