/* SPDX-License-Identifier: GPL-2.0+ */ /* * Based on 5.2.0, Family Programming Guide (Sept 30, 2020) * * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company. */ #ifndef HAVE_IDT8A340_REG #define HAVE_IDT8A340_REG #define PAGE_ADDR_BASE … #define PAGE_ADDR … #define HW_REVISION … #define REV_ID … #define HW_DPLL_0 … #define HW_DPLL_1 … #define HW_DPLL_2 … #define HW_DPLL_3 … #define HW_DPLL_4 … #define HW_DPLL_5 … #define HW_DPLL_6 … #define HW_DPLL_7 … #define HW_DPLL_TOD_SW_TRIG_ADDR__0 … #define HW_DPLL_TOD_CTRL_1 … #define HW_DPLL_TOD_CTRL_2 … #define HW_DPLL_TOD_OVR__0 … #define HW_DPLL_TOD_OUT_0__0 … #define HW_Q0_Q1_CH_SYNC_CTRL_0 … #define HW_Q0_Q1_CH_SYNC_CTRL_1 … #define HW_Q2_Q3_CH_SYNC_CTRL_0 … #define HW_Q2_Q3_CH_SYNC_CTRL_1 … #define HW_Q4_Q5_CH_SYNC_CTRL_0 … #define HW_Q4_Q5_CH_SYNC_CTRL_1 … #define HW_Q6_Q7_CH_SYNC_CTRL_0 … #define HW_Q6_Q7_CH_SYNC_CTRL_1 … #define HW_Q8_CH_SYNC_CTRL_0 … #define HW_Q8_CH_SYNC_CTRL_1 … #define HW_Q9_CH_SYNC_CTRL_0 … #define HW_Q9_CH_SYNC_CTRL_1 … #define HW_Q10_CH_SYNC_CTRL_0 … #define HW_Q10_CH_SYNC_CTRL_1 … #define HW_Q11_CH_SYNC_CTRL_0 … #define HW_Q11_CH_SYNC_CTRL_1 … #define SYNC_SOURCE_DPLL0_TOD_PPS … #define SYNC_SOURCE_DPLL1_TOD_PPS … #define SYNC_SOURCE_DPLL2_TOD_PPS … #define SYNC_SOURCE_DPLL3_TOD_PPS … #define SYNCTRL1_MASTER_SYNC_RST … #define SYNCTRL1_MASTER_SYNC_TRIG … #define SYNCTRL1_TOD_SYNC_TRIG … #define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG … #define SYNCTRL1_FBDIV_SYNC_TRIG … #define SYNCTRL1_Q1_DIV_SYNC_TRIG … #define SYNCTRL1_Q0_DIV_SYNC_TRIG … #define HW_Q8_CTRL_SPARE … #define HW_Q11_CTRL_SPARE … /* * Select FOD5 as sync_trigger for Q8 divider. * Transition from logic zero to one * sets trigger to sync Q8 divider. * * Unused when FOD4 is driving Q8 divider (normal operation). */ #define Q9_TO_Q8_SYNC_TRIG … /* * Enable FOD5 as driver for clock and sync for Q8 divider. * Enable fanout buffer for FOD5. * * Unused when FOD4 is driving Q8 divider (normal operation). */ #define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK … /* * Select FOD6 as sync_trigger for Q11 divider. * Transition from logic zero to one * sets trigger to sync Q11 divider. * * Unused when FOD7 is driving Q11 divider (normal operation). */ #define Q10_TO_Q11_SYNC_TRIG … /* * Enable FOD6 as driver for clock and sync for Q11 divider. * Enable fanout buffer for FOD6. * * Unused when FOD7 is driving Q11 divider (normal operation). */ #define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK … #define RESET_CTRL … #define SM_RESET … #define SM_RESET_V520 … #define SM_RESET_CMD … #define GENERAL_STATUS … #define BOOT_STATUS … #define HW_REV_ID … #define BOND_ID … #define HW_CSR_ID … #define HW_IRQ_ID … #define MAJ_REL … #define MIN_REL … #define HOTFIX_REL … #define PIPELINE_ID … #define BUILD_ID … #define JTAG_DEVICE_ID … #define PRODUCT_ID … #define OTP_SCSR_CONFIG_SELECT … #define STATUS … #define DPLL0_STATUS … #define DPLL1_STATUS … #define DPLL2_STATUS … #define DPLL3_STATUS … #define DPLL4_STATUS … #define DPLL5_STATUS … #define DPLL6_STATUS … #define DPLL7_STATUS … #define DPLL_SYS_STATUS … #define DPLL_SYS_APLL_STATUS … #define DPLL0_FILTER_STATUS … #define DPLL1_FILTER_STATUS … #define DPLL2_FILTER_STATUS … #define DPLL3_FILTER_STATUS … #define DPLL4_FILTER_STATUS … #define DPLL5_FILTER_STATUS … #define DPLL6_FILTER_STATUS … #define DPLL7_FILTER_STATUS … #define DPLLSYS_FILTER_STATUS … #define USER_GPIO0_TO_7_STATUS … #define USER_GPIO8_TO_15_STATUS … #define GPIO_USER_CONTROL … #define GPIO0_TO_7_OUT … #define GPIO8_TO_15_OUT … #define GPIO0_TO_7_OUT_V520 … #define GPIO8_TO_15_OUT_V520 … #define STICKY_STATUS_CLEAR … #define GPIO_TOD_NOTIFICATION_CLEAR … #define ALERT_CFG … #define SYS_DPLL_XO … #define SYS_APLL … #define INPUT_0 … #define INPUT_1 … #define INPUT_2 … #define INPUT_3 … #define INPUT_4 … #define INPUT_5 … #define INPUT_6 … #define INPUT_7 … #define INPUT_8 … #define INPUT_9 … #define INPUT_10 … #define INPUT_11 … #define INPUT_12 … #define INPUT_13 … #define INPUT_14 … #define INPUT_15 … #define REF_MON_0 … #define REF_MON_1 … #define REF_MON_2 … #define REF_MON_3 … #define REF_MON_4 … #define REF_MON_5 … #define REF_MON_6 … #define REF_MON_7 … #define REF_MON_8 … #define REF_MON_9 … #define REF_MON_10 … #define REF_MON_11 … #define REF_MON_12 … #define REF_MON_13 … #define REF_MON_14 … #define REF_MON_15 … #define DPLL_0 … #define DPLL_CTRL_REG_0 … #define DPLL_CTRL_REG_1 … #define DPLL_CTRL_REG_2 … #define DPLL_TOD_SYNC_CFG … #define DPLL_COMBO_SLAVE_CFG_0 … #define DPLL_COMBO_SLAVE_CFG_1 … #define DPLL_SLAVE_REF_CFG … #define DPLL_REF_MODE … #define DPLL_PHASE_MEASUREMENT_CFG … #define DPLL_MODE … #define DPLL_MODE_V520 … #define DPLL_1 … #define DPLL_2 … #define DPLL_2_V520 … #define DPLL_3 … #define DPLL_4 … #define DPLL_4_V520 … #define DPLL_5 … #define DPLL_6 … #define DPLL_6_V520 … #define DPLL_7 … #define SYS_DPLL … #define SYS_DPLL_V520 … #define DPLL_CTRL_0 … #define DPLL_CTRL_DPLL_MANU_REF_CFG … #define DPLL_CTRL_DPLL_FOD_FREQ … #define DPLL_CTRL_COMBO_MASTER_CFG … #define DPLL_CTRL_1 … #define DPLL_CTRL_2 … #define DPLL_CTRL_3 … #define DPLL_CTRL_4 … #define DPLL_CTRL_5 … #define DPLL_CTRL_6 … #define DPLL_CTRL_7 … #define SYS_DPLL_CTRL … #define DPLL_PHASE_0 … /* Signed 42-bit FFO in units of 2^(-53) */ #define DPLL_WR_PHASE … #define DPLL_PHASE_1 … #define DPLL_PHASE_2 … #define DPLL_PHASE_3 … #define DPLL_PHASE_4 … #define DPLL_PHASE_5 … #define DPLL_PHASE_6 … #define DPLL_PHASE_7 … #define DPLL_FREQ_0 … /* Signed 42-bit FFO in units of 2^(-53) */ #define DPLL_WR_FREQ … #define DPLL_FREQ_1 … #define DPLL_FREQ_2 … #define DPLL_FREQ_3 … #define DPLL_FREQ_4 … #define DPLL_FREQ_5 … #define DPLL_FREQ_6 … #define DPLL_FREQ_7 … #define DPLL_PHASE_PULL_IN_0 … #define PULL_IN_OFFSET … #define PULL_IN_SLOPE_LIMIT … #define PULL_IN_CTRL … #define DPLL_PHASE_PULL_IN_1 … #define DPLL_PHASE_PULL_IN_2 … #define DPLL_PHASE_PULL_IN_3 … #define DPLL_PHASE_PULL_IN_4 … #define DPLL_PHASE_PULL_IN_5 … #define DPLL_PHASE_PULL_IN_6 … #define DPLL_PHASE_PULL_IN_7 … #define GPIO_CFG … #define GPIO_CFG_GBL … #define GPIO_0 … #define GPIO_DCO_INC_DEC … #define GPIO_OUT_CTRL_0 … #define GPIO_OUT_CTRL_1 … #define GPIO_TOD_TRIG … #define GPIO_DPLL_INDICATOR … #define GPIO_LOS_INDICATOR … #define GPIO_REF_INPUT_DSQ_0 … #define GPIO_REF_INPUT_DSQ_1 … #define GPIO_REF_INPUT_DSQ_2 … #define GPIO_REF_INPUT_DSQ_3 … #define GPIO_MAN_CLK_SEL_0 … #define GPIO_MAN_CLK_SEL_1 … #define GPIO_MAN_CLK_SEL_2 … #define GPIO_SLAVE … #define GPIO_ALERT_OUT_CFG … #define GPIO_TOD_NOTIFICATION_CFG … #define GPIO_CTRL … #define GPIO_CTRL_V520 … #define GPIO_1 … #define GPIO_2 … #define GPIO_3 … #define GPIO_4 … #define GPIO_5 … #define GPIO_6 … #define GPIO_7 … #define GPIO_8 … #define GPIO_9 … #define GPIO_10 … #define GPIO_11 … #define GPIO_12 … #define GPIO_13 … #define GPIO_14 … #define GPIO_15 … #define OUT_DIV_MUX … #define OUTPUT_0 … #define OUTPUT_0_V520 … /* FOD frequency output divider value */ #define OUT_DIV … #define OUT_DUTY_CYCLE_HIGH … #define OUT_CTRL_0 … #define OUT_CTRL_1 … /* Phase adjustment in FOD cycles */ #define OUT_PHASE_ADJ … #define OUTPUT_1 … #define OUTPUT_1_V520 … #define OUTPUT_2 … #define OUTPUT_2_V520 … #define OUTPUT_3 … #define OUTPUT_3_V520 … #define OUTPUT_4 … #define OUTPUT_4_V520 … #define OUTPUT_5 … #define OUTPUT_5_V520 … #define OUTPUT_6 … #define OUTPUT_6_V520 … #define OUTPUT_7 … #define OUTPUT_7_V520 … #define OUTPUT_8 … #define OUTPUT_8_V520 … #define OUTPUT_9 … #define OUTPUT_9_V520 … #define OUTPUT_10 … #define OUTPUT_10_V520 … #define OUTPUT_11 … #define OUTPUT_11_V520 … #define SERIAL … #define SERIAL_V520 … #define PWM_ENCODER_0 … #define PWM_ENCODER_1 … #define PWM_ENCODER_2 … #define PWM_ENCODER_3 … #define PWM_ENCODER_4 … #define PWM_ENCODER_5 … #define PWM_ENCODER_6 … #define PWM_ENCODER_7 … #define PWM_DECODER_0 … #define PWM_DECODER_1 … #define PWM_DECODER_1_V520 … #define PWM_DECODER_2 … #define PWM_DECODER_2_V520 … #define PWM_DECODER_3 … #define PWM_DECODER_3_V520 … #define PWM_DECODER_4 … #define PWM_DECODER_4_V520 … #define PWM_DECODER_5 … #define PWM_DECODER_5_V520 … #define PWM_DECODER_6 … #define PWM_DECODER_6_V520 … #define PWM_DECODER_7 … #define PWM_DECODER_7_V520 … #define PWM_DECODER_8 … #define PWM_DECODER_8_V520 … #define PWM_DECODER_9 … #define PWM_DECODER_9_V520 … #define PWM_DECODER_10 … #define PWM_DECODER_10_V520 … #define PWM_DECODER_11 … #define PWM_DECODER_11_V520 … #define PWM_DECODER_12 … #define PWM_DECODER_12_V520 … #define PWM_DECODER_13 … #define PWM_DECODER_13_V520 … #define PWM_DECODER_14 … #define PWM_DECODER_14_V520 … #define PWM_DECODER_15 … #define PWM_DECODER_15_V520 … #define PWM_USER_DATA … #define PWM_USER_DATA_V520 … #define TOD_0 … #define TOD_0_V520 … /* Enable TOD counter, output channel sync and even-PPS mode */ #define TOD_CFG … #define TOD_CFG_V520 … #define TOD_1 … #define TOD_1_V520 … #define TOD_2 … #define TOD_2_V520 … #define TOD_3 … #define TOD_3_V520 … #define TOD_WRITE_0 … #define TOD_WRITE_0_V520 … /* 8-bit subns, 32-bit ns, 48-bit seconds */ #define TOD_WRITE … /* Counter increments after TOD write is completed */ #define TOD_WRITE_COUNTER … /* TOD write trigger configuration */ #define TOD_WRITE_SELECT_CFG_0 … /* TOD write trigger selection */ #define TOD_WRITE_CMD … #define TOD_WRITE_1 … #define TOD_WRITE_1_V520 … #define TOD_WRITE_2 … #define TOD_WRITE_2_V520 … #define TOD_WRITE_3 … #define TOD_WRITE_3_V520 … #define TOD_READ_PRIMARY_0 … #define TOD_READ_PRIMARY_0_V520 … /* 8-bit subns, 32-bit ns, 48-bit seconds */ #define TOD_READ_PRIMARY_BASE … /* Counter increments after TOD write is completed */ #define TOD_READ_PRIMARY_COUNTER … /* Read trigger configuration */ #define TOD_READ_PRIMARY_SEL_CFG_0 … /* Read trigger selection */ #define TOD_READ_PRIMARY_CMD … #define TOD_READ_PRIMARY_CMD_V520 … #define TOD_READ_PRIMARY_1 … #define TOD_READ_PRIMARY_1_V520 … #define TOD_READ_PRIMARY_2 … #define TOD_READ_PRIMARY_2_V520 … #define TOD_READ_PRIMARY_3 … #define TOD_READ_PRIMARY_3_V520 … #define TOD_READ_SECONDARY_0 … #define TOD_READ_SECONDARY_0_V520 … /* 8-bit subns, 32-bit ns, 48-bit seconds */ #define TOD_READ_SECONDARY_BASE … /* Counter increments after TOD write is completed */ #define TOD_READ_SECONDARY_COUNTER … /* Read trigger configuration */ #define TOD_READ_SECONDARY_SEL_CFG_0 … /* Read trigger selection */ #define TOD_READ_SECONDARY_CMD … #define TOD_READ_SECONDARY_CMD_V520 … #define TOD_READ_SECONDARY_1 … #define TOD_READ_SECONDARY_1_V520 … #define TOD_READ_SECONDARY_2 … #define TOD_READ_SECONDARY_2_V520 … #define TOD_READ_SECONDARY_3 … #define TOD_READ_SECONDARY_3_V520 … #define OUTPUT_TDC_CFG … #define OUTPUT_TDC_CFG_V520 … #define OUTPUT_TDC_0 … #define OUTPUT_TDC_1 … #define OUTPUT_TDC_2 … #define OUTPUT_TDC_3 … #define INPUT_TDC … #define SCRATCH … #define SCRATCH_V520 … #define EEPROM … #define EEPROM_V520 … #define OTP … #define BYTE … /* Bit definitions for the MAJ_REL register */ #define MAJOR_SHIFT … #define MAJOR_MASK … #define PR_BUILD … /* Bit definitions for the USER_GPIO0_TO_7_STATUS register */ #define GPIO0_LEVEL … #define GPIO1_LEVEL … #define GPIO2_LEVEL … #define GPIO3_LEVEL … #define GPIO4_LEVEL … #define GPIO5_LEVEL … #define GPIO6_LEVEL … #define GPIO7_LEVEL … /* Bit definitions for the USER_GPIO8_TO_15_STATUS register */ #define GPIO8_LEVEL … #define GPIO9_LEVEL … #define GPIO10_LEVEL … #define GPIO11_LEVEL … #define GPIO12_LEVEL … #define GPIO13_LEVEL … #define GPIO14_LEVEL … #define GPIO15_LEVEL … /* Bit definitions for the GPIO0_TO_7_OUT register */ #define GPIO0_DRIVE_LEVEL … #define GPIO1_DRIVE_LEVEL … #define GPIO2_DRIVE_LEVEL … #define GPIO3_DRIVE_LEVEL … #define GPIO4_DRIVE_LEVEL … #define GPIO5_DRIVE_LEVEL … #define GPIO6_DRIVE_LEVEL … #define GPIO7_DRIVE_LEVEL … /* Bit definitions for the GPIO8_TO_15_OUT register */ #define GPIO8_DRIVE_LEVEL … #define GPIO9_DRIVE_LEVEL … #define GPIO10_DRIVE_LEVEL … #define GPIO11_DRIVE_LEVEL … #define GPIO12_DRIVE_LEVEL … #define GPIO13_DRIVE_LEVEL … #define GPIO14_DRIVE_LEVEL … #define GPIO15_DRIVE_LEVEL … /* Bit definitions for the DPLL_TOD_SYNC_CFG register */ #define TOD_SYNC_SOURCE_SHIFT … #define TOD_SYNC_SOURCE_MASK … #define TOD_SYNC_EN … /* Bit definitions for the DPLL_MODE register */ #define WRITE_TIMER_MODE … #define PLL_MODE_SHIFT … #define PLL_MODE_MASK … #define STATE_MODE_SHIFT … #define STATE_MODE_MASK … /* Bit definitions for the DPLL_MANU_REF_CFG register */ #define MANUAL_REFERENCE_SHIFT … #define MANUAL_REFERENCE_MASK … /* Bit definitions for the GPIO_CFG_GBL register */ #define SUPPLY_MODE_SHIFT … #define SUPPLY_MODE_MASK … /* Bit definitions for the GPIO_DCO_INC_DEC register */ #define INCDEC_DPLL_INDEX_SHIFT … #define INCDEC_DPLL_INDEX_MASK … /* Bit definitions for the GPIO_OUT_CTRL_0 register */ #define CTRL_OUT_0 … #define CTRL_OUT_1 … #define CTRL_OUT_2 … #define CTRL_OUT_3 … #define CTRL_OUT_4 … #define CTRL_OUT_5 … #define CTRL_OUT_6 … #define CTRL_OUT_7 … /* Bit definitions for the GPIO_OUT_CTRL_1 register */ #define CTRL_OUT_8 … #define CTRL_OUT_9 … #define CTRL_OUT_10 … #define CTRL_OUT_11 … #define CTRL_OUT_12 … #define CTRL_OUT_13 … #define CTRL_OUT_14 … #define CTRL_OUT_15 … /* Bit definitions for the GPIO_TOD_TRIG register */ #define TOD_TRIG_0 … #define TOD_TRIG_1 … #define TOD_TRIG_2 … #define TOD_TRIG_3 … /* Bit definitions for the GPIO_DPLL_INDICATOR register */ #define IND_DPLL_INDEX_SHIFT … #define IND_DPLL_INDEX_MASK … /* Bit definitions for the GPIO_LOS_INDICATOR register */ #define REFMON_INDEX_SHIFT … #define REFMON_INDEX_MASK … /* Active level of LOS indicator, 0=low 1=high */ #define ACTIVE_LEVEL … /* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */ #define DSQ_INP_0 … #define DSQ_INP_1 … #define DSQ_INP_2 … #define DSQ_INP_3 … #define DSQ_INP_4 … #define DSQ_INP_5 … #define DSQ_INP_6 … #define DSQ_INP_7 … /* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */ #define DSQ_INP_8 … #define DSQ_INP_9 … #define DSQ_INP_10 … #define DSQ_INP_11 … #define DSQ_INP_12 … #define DSQ_INP_13 … #define DSQ_INP_14 … #define DSQ_INP_15 … /* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */ #define DSQ_DPLL_0 … #define DSQ_DPLL_1 … #define DSQ_DPLL_2 … #define DSQ_DPLL_3 … #define DSQ_DPLL_4 … #define DSQ_DPLL_5 … #define DSQ_DPLL_6 … #define DSQ_DPLL_7 … /* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */ #define DSQ_DPLL_SYS … #define GPIO_DSQ_LEVEL … /* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */ #define DPLL_TOD_SHIFT … #define DPLL_TOD_MASK … #define TOD_READ_SECONDARY … #define GPIO_ASSERT_LEVEL … /* Bit definitions for the GPIO_CTRL register */ #define GPIO_FUNCTION_EN … #define GPIO_CMOS_OD_MODE … #define GPIO_CONTROL_DIR … #define GPIO_PU_PD_MODE … #define GPIO_FUNCTION_SHIFT … #define GPIO_FUNCTION_MASK … /* Bit definitions for the OUT_CTRL_1 register */ #define OUT_SYNC_DISABLE … #define SQUELCH_VALUE … #define SQUELCH_DISABLE … #define PAD_VDDO_SHIFT … #define PAD_VDDO_MASK … #define PAD_CMOSDRV_SHIFT … #define PAD_CMOSDRV_MASK … /* Bit definitions for the TOD_CFG register */ #define TOD_EVEN_PPS_MODE … #define TOD_OUT_SYNC_ENABLE … #define TOD_ENABLE … /* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */ #define WR_PWM_DECODER_INDEX_SHIFT … #define WR_PWM_DECODER_INDEX_MASK … #define WR_REF_INDEX_SHIFT … #define WR_REF_INDEX_MASK … /* Bit definitions for the TOD_WRITE_CMD register */ #define TOD_WRITE_SELECTION_SHIFT … #define TOD_WRITE_SELECTION_MASK … /* 4.8.7 */ #define TOD_WRITE_TYPE_SHIFT … #define TOD_WRITE_TYPE_MASK … /* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */ #define RD_PWM_DECODER_INDEX_SHIFT … #define RD_PWM_DECODER_INDEX_MASK … #define RD_REF_INDEX_SHIFT … #define RD_REF_INDEX_MASK … /* Bit definitions for the TOD_READ_PRIMARY_CMD register */ #define TOD_READ_TRIGGER_MODE … #define TOD_READ_TRIGGER_SHIFT … #define TOD_READ_TRIGGER_MASK … /* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */ #define COMBO_MASTER_HOLD … /* Bit definitions for DPLL_SYS_STATUS register */ #define DPLL_SYS_STATE_MASK … /* Bit definitions for SYS_APLL_STATUS register */ #define SYS_APLL_LOSS_LOCK_LIVE_MASK … #define SYS_APLL_LOSS_LOCK_LIVE_LOCKED … #define SYS_APLL_LOSS_LOCK_LIVE_UNLOCKED … /* Bit definitions for the DPLL0_STATUS register */ #define DPLL_STATE_MASK … #define DPLL_STATE_SHIFT … /* Values of DPLL_N.DPLL_MODE.PLL_MODE */ enum pll_mode { … }; /* Values of DPLL_CTRL_n.DPLL_MANU_REF_CFG.MANUAL_REFERENCE */ enum manual_reference { … }; enum hw_tod_write_trig_sel { … }; enum scsr_read_trig_sel { … }; /* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */ enum dpll_state { … }; /* 4.8.7 only */ enum scsr_tod_write_trig_sel { … }; /* 4.8.7 only */ enum scsr_tod_write_type_sel { … }; #endif
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