/* SPDX-License-Identifier: GPL-2.0+ */ /* * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and * synchronization devices. * * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. */ #ifndef PTP_IDTCLOCKMATRIX_H #define PTP_IDTCLOCKMATRIX_H #include <linux/ktime.h> #include <linux/mfd/idt8a340_reg.h> #include <linux/ptp_clock.h> #include <linux/regmap.h> #define FW_FILENAME … #define MAX_TOD … #define MAX_PLL … #define MAX_REF_CLK … #define MAX_ABS_WRITE_PHASE_NANOSECONDS … #define TOD_MASK_ADDR … #define DEFAULT_TOD_MASK … #define SET_U16_LSB(orig, val8) … #define SET_U16_MSB(orig, val8) … #define TOD0_PTP_PLL_ADDR … #define TOD1_PTP_PLL_ADDR … #define TOD2_PTP_PLL_ADDR … #define TOD3_PTP_PLL_ADDR … #define TOD0_OUT_ALIGN_MASK_ADDR … #define TOD1_OUT_ALIGN_MASK_ADDR … #define TOD2_OUT_ALIGN_MASK_ADDR … #define TOD3_OUT_ALIGN_MASK_ADDR … #define DEFAULT_OUTPUT_MASK_PLL0 … #define DEFAULT_OUTPUT_MASK_PLL1 … #define DEFAULT_OUTPUT_MASK_PLL2 … #define DEFAULT_OUTPUT_MASK_PLL3 … #define DEFAULT_TOD0_PTP_PLL … #define DEFAULT_TOD1_PTP_PLL … #define DEFAULT_TOD2_PTP_PLL … #define DEFAULT_TOD3_PTP_PLL … #define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED … #define PHASE_PULL_IN_THRESHOLD_NS … #define TOD_WRITE_OVERHEAD_COUNT_MAX … #define TOD_BYTE_COUNT … #define LOCK_TIMEOUT_MS … #define LOCK_POLL_INTERVAL_MS … #define IDTCM_MAX_WRITE_COUNT … #define PHASE_PULL_IN_MAX_PPB … #define PHASE_PULL_IN_MIN_THRESHOLD_NS … /* * Return register address based on passed in firmware version */ #define IDTCM_FW_REG(FW, VER, REG) … enum fw_version { … }; /* PTP PLL Mode */ enum ptp_pll_mode { … }; struct idtcm; struct idtcm_channel { … }; struct idtcm { … }; struct idtcm_fwrc { … } __packed; #endif /* PTP_IDTCLOCKMATRIX_H */
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