/* SPDX-License-Identifier: GPL-2.0+ */ /* * Register Map - Based on AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf * * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company. */ #ifndef HAVE_IDT82P33_REG #define HAVE_IDT82P33_REG #define REG_ADDR(page, offset) … /* Register address */ #define DPLL1_TOD_CNFG … #define DPLL2_TOD_CNFG … #define DPLL1_TOD_STS … #define DPLL2_TOD_STS … #define DPLL1_TOD_TRIGGER … #define DPLL2_TOD_TRIGGER … #define DPLL1_OPERATING_MODE_CNFG … #define DPLL2_OPERATING_MODE_CNFG … #define DPLL1_HOLDOVER_FREQ_CNFG … #define DPLL2_HOLDOVER_FREQ_CNFG … #define DPLL1_PHASE_OFFSET_CNFG … #define DPLL2_PHASE_OFFSET_CNFG … #define DPLL1_SYNC_EDGE_CNFG … #define DPLL2_SYNC_EDGE_CNFG … #define DPLL1_INPUT_MODE_CNFG … #define DPLL2_INPUT_MODE_CNFG … #define DPLL1_OPERATING_STS … #define DPLL2_OPERATING_STS … #define DPLL1_CURRENT_FREQ_STS … #define DPLL2_CURRENT_FREQ_STS … #define REG_SOFT_RESET … #define OUT_MUX_CNFG(outn) … #define TOD_TRIGGER(wr_trig, rd_trig) … /* Register bit definitions */ #define SYNC_TOD … #define PH_OFFSET_EN … #define SQUELCH_ENABLE … /* Bit definitions for the DPLL_MODE register */ #define PLL_MODE_SHIFT … #define PLL_MODE_MASK … #define COMBO_MODE_EN … #define COMBO_MODE_SHIFT … #define COMBO_MODE_MASK … /* Bit definitions for DPLL_OPERATING_STS register */ #define OPERATING_STS_MASK … #define OPERATING_STS_SHIFT … /* Bit definitions for DPLL_TOD_TRIGGER register */ #define READ_TRIGGER_MASK … #define READ_TRIGGER_SHIFT … #define WRITE_TRIGGER_MASK … #define WRITE_TRIGGER_SHIFT … /* Bit definitions for REG_SOFT_RESET register */ #define SOFT_RESET_EN … enum pll_mode { … }; enum hw_tod_trig_sel { … }; /** @brief Enumerated type listing DPLL operational modes */ enum dpll_state { … }; #endif
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