/* SPDX-License-Identifier: GPL-2.0+ */ /* * PTP hardware clock driver for the IDT 82P33XXX family of clocks. * * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. */ #ifndef PTP_IDT82P33_H #define PTP_IDT82P33_H #include <linux/ktime.h> #include <linux/mfd/idt82p33_reg.h> #include <linux/regmap.h> #define FW_FILENAME … #define MAX_PHC_PLL … #define MAX_TRIG_CLK … #define MAX_PER_OUT … #define TOD_BYTE_COUNT … #define DCO_MAX_PPB … #define MAX_MEASURMENT_COUNT … #define SNAP_THRESHOLD_NS … #define IMMEDIATE_SNAP_THRESHOLD_NS … #define DDCO_THRESHOLD_NS … #define IDT82P33_MAX_WRITE_COUNT … #define PLLMASK_ADDR_HI … #define PLLMASK_ADDR_LO … #define PLL0_OUTMASK_ADDR_HI … #define PLL0_OUTMASK_ADDR_LO … #define PLL1_OUTMASK_ADDR_HI … #define PLL1_OUTMASK_ADDR_LO … #define PLL2_OUTMASK_ADDR_HI … #define PLL2_OUTMASK_ADDR_LO … #define PLL3_OUTMASK_ADDR_HI … #define PLL3_OUTMASK_ADDR_LO … #define DEFAULT_PLL_MASK … #define DEFAULT_OUTPUT_MASK_PLL0 … #define DEFAULT_OUTPUT_MASK_PLL1 … /** * @brief Maximum absolute value for write phase offset in nanoseconds */ #define WRITE_PHASE_OFFSET_LIMIT … /** @brief Phase offset resolution * * DPLL phase offset = 10^15 fs / ( System Clock * 2^13) * = 10^15 fs / ( 1638400000 * 2^23) * = 74.5058059692382 fs */ #define IDT_T0DPLL_PHASE_RESOL … /* PTP Hardware Clock interface */ struct idt82p33_channel { … }; struct idt82p33 { … }; /* firmware interface */ struct idt82p33_fwrc { … } __packed; #endif /* PTP_IDT82P33_H */
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