// SPDX-License-Identifier: GPL-2.0+ /* * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and * synchronization devices. * * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. */ #include <linux/firmware.h> #include <linux/platform_device.h> #include <linux/module.h> #include <linux/ptp_clock_kernel.h> #include <linux/delay.h> #include <linux/jiffies.h> #include <linux/kernel.h> #include <linux/timekeeping.h> #include <linux/string.h> #include <linux/of.h> #include <linux/mfd/rsmu.h> #include <linux/mfd/idt8a340_reg.h> #include <asm/unaligned.h> #include "ptp_private.h" #include "ptp_clockmatrix.h" MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_VERSION(…) …; MODULE_LICENSE(…) …; /* * The name of the firmware file to be loaded * over-rides any automatic selection */ static char *firmware; module_param(firmware, charp, 0); #define SETTIME_CORRECTION … #define EXTTS_PERIOD_MS … static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm); static inline int idtcm_read(struct idtcm *idtcm, u16 module, u16 regaddr, u8 *buf, u16 count) { … } static inline int idtcm_write(struct idtcm *idtcm, u16 module, u16 regaddr, u8 *buf, u16 count) { … } static int contains_full_configuration(struct idtcm *idtcm, const struct firmware *fw) { … } static int char_array_to_timespec(u8 *buf, u8 count, struct timespec64 *ts) { … } static int timespec_to_char_array(struct timespec64 const *ts, u8 *buf, u8 count) { … } static int idtcm_strverscmp(const char *version1, const char *version2) { … } static enum fw_version idtcm_fw_version(const char *version) { … } static int clear_boot_status(struct idtcm *idtcm) { … } static int read_boot_status(struct idtcm *idtcm, u32 *status) { … } static int wait_for_boot_status_ready(struct idtcm *idtcm) { … } static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref) { … } static bool is_single_shot(u8 mask) { … } static int idtcm_extts_enable(struct idtcm_channel *channel, struct ptp_clock_request *rq, int on) { … } static int read_sys_apll_status(struct idtcm *idtcm, u8 *status) { … } static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status) { … } static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm) { … } static void wait_for_chip_ready(struct idtcm *idtcm) { … } static int _idtcm_gettime_triggered(struct idtcm_channel *channel, struct timespec64 *ts) { … } static int _idtcm_gettime(struct idtcm_channel *channel, struct timespec64 *ts, u8 timeout) { … } static int idtcm_extts_check_channel(struct idtcm *idtcm, u8 todn) { … } static int _idtcm_gettime_immediate(struct idtcm_channel *channel, struct timespec64 *ts) { … } static int _sync_pll_output(struct idtcm *idtcm, u8 pll, u8 sync_src, u8 qn, u8 qn_plus_1) { … } static int idtcm_sync_pps_output(struct idtcm_channel *channel) { … } static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel, struct timespec64 const *ts, enum hw_tod_write_trig_sel wr_trig) { … } static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel, struct timespec64 const *ts, enum scsr_tod_write_trig_sel wr_trig, enum scsr_tod_write_type_sel wr_type) { … } static int get_output_base_addr(enum fw_version ver, u8 outn) { … } static int _idtcm_settime_deprecated(struct idtcm_channel *channel, struct timespec64 const *ts) { … } static int _idtcm_settime(struct idtcm_channel *channel, struct timespec64 const *ts, enum scsr_tod_write_type_sel wr_type) { … } static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel, s32 offset_ns) { … } static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel, u32 max_ffo_ppb) { … } static int idtcm_start_phase_pull_in(struct idtcm_channel *channel) { … } static int do_phase_pull_in_fw(struct idtcm_channel *channel, s32 offset_ns, u32 max_ffo_ppb) { … } static int set_tod_write_overhead(struct idtcm_channel *channel) { … } static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta) { … } static int idtcm_state_machine_reset(struct idtcm *idtcm) { … } static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id) { … } static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id) { … } static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major) { … } static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor) { … } static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix) { … } static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm, u8 *config_select) { … } static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val) { … } static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll) { … } static int check_and_set_masks(struct idtcm *idtcm, u16 regaddr, u8 val) { … } static void display_pll_and_masks(struct idtcm *idtcm) { … } static int idtcm_load_firmware(struct idtcm *idtcm, struct device *dev) { … } static int idtcm_output_enable(struct idtcm_channel *channel, bool enable, unsigned int outn) { … } static int idtcm_perout_enable(struct idtcm_channel *channel, struct ptp_perout_request *perout, bool enable) { … } static int idtcm_get_pll_mode(struct idtcm_channel *channel, enum pll_mode *mode) { … } static int idtcm_set_pll_mode(struct idtcm_channel *channel, enum pll_mode mode) { … } static int idtcm_get_manual_reference(struct idtcm_channel *channel, enum manual_reference *ref) { … } static int idtcm_set_manual_reference(struct idtcm_channel *channel, enum manual_reference ref) { … } static int configure_dpll_mode_write_frequency(struct idtcm_channel *channel) { … } static int configure_dpll_mode_write_phase(struct idtcm_channel *channel) { … } static int configure_manual_reference_write_frequency(struct idtcm_channel *channel) { … } static int configure_manual_reference_write_phase(struct idtcm_channel *channel) { … } static int idtcm_stop_phase_pull_in(struct idtcm_channel *channel) { … } static long idtcm_work_handler(struct ptp_clock_info *ptp) { … } static s32 phase_pull_in_scaled_ppm(s32 current_ppm, s32 phase_pull_in_ppb) { … } static int do_phase_pull_in_sw(struct idtcm_channel *channel, s32 delta_ns, u32 max_ffo_ppb) { … } static int initialize_operating_mode_with_manual_reference(struct idtcm_channel *channel, enum manual_reference ref) { … } static int initialize_operating_mode_with_pll_mode(struct idtcm_channel *channel, enum pll_mode mode) { … } static int initialize_dco_operating_mode(struct idtcm_channel *channel) { … } /* PTP Hardware Clock interface */ /* * Maximum absolute value for write phase offset in nanoseconds * * Destination signed register is 32-bit register in resolution of 50ps * * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350 ps * Represent 107374182350 ps as 107374182 ns */ static s32 idtcm_getmaxphase(struct ptp_clock_info *ptp __always_unused) { … } /* * Internal function for implementing support for write phase offset * * @channel: channel * @delta_ns: delta in nanoseconds */ static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns) { … } static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm) { … } static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) { … } static int idtcm_settime_deprecated(struct ptp_clock_info *ptp, const struct timespec64 *ts) { … } static int idtcm_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts) { … } static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta) { … } static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) { … } static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta) { … } static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) { … } static int idtcm_enable(struct ptp_clock_info *ptp, struct ptp_clock_request *rq, int on) { … } static int idtcm_enable_tod(struct idtcm_channel *channel) { … } static void idtcm_set_version_info(struct idtcm *idtcm) { … } static int idtcm_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, enum ptp_pin_function func, unsigned int chan) { … } static struct ptp_pin_desc pin_config[MAX_TOD][MAX_REF_CLK]; static const struct ptp_clock_info idtcm_caps = …; static const struct ptp_clock_info idtcm_caps_deprecated = …; static int configure_channel_pll(struct idtcm_channel *channel) { … } /* * Compensate for the PTP DCO input-to-output delay. * This delay is 18 FOD cycles. */ static u32 idtcm_get_dco_delay(struct idtcm_channel *channel) { … } static int configure_channel_tod(struct idtcm_channel *channel, u32 index) { … } static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) { … } static int idtcm_enable_extts_channel(struct idtcm *idtcm, u32 index) { … } static void idtcm_extts_check(struct work_struct *work) { … } static void ptp_clock_unregister_all(struct idtcm *idtcm) { … } static void set_default_masks(struct idtcm *idtcm) { … } static int idtcm_probe(struct platform_device *pdev) { … } static void idtcm_remove(struct platform_device *pdev) { … } static struct platform_driver idtcm_driver = …; module_platform_driver(…) …;
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