/* SPDX-License-Identifier: GPL-2.0-only */ /* * 1-Wire implementation for the ds2780 chip * * Copyright (C) 2010 Indesign, LLC * * Author: Clifton Barnes <[email protected]> * * Based on w1-ds2760 driver */ #ifndef _W1_DS2780_H #define _W1_DS2780_H /* Function commands */ #define W1_DS2780_READ_DATA … #define W1_DS2780_WRITE_DATA … #define W1_DS2780_COPY_DATA … #define W1_DS2780_RECALL_DATA … #define W1_DS2780_LOCK … /* Register map */ /* Register 0x00 Reserved */ #define DS2780_STATUS_REG … #define DS2780_RAAC_MSB_REG … #define DS2780_RAAC_LSB_REG … #define DS2780_RSAC_MSB_REG … #define DS2780_RSAC_LSB_REG … #define DS2780_RARC_REG … #define DS2780_RSRC_REG … #define DS2780_IAVG_MSB_REG … #define DS2780_IAVG_LSB_REG … #define DS2780_TEMP_MSB_REG … #define DS2780_TEMP_LSB_REG … #define DS2780_VOLT_MSB_REG … #define DS2780_VOLT_LSB_REG … #define DS2780_CURRENT_MSB_REG … #define DS2780_CURRENT_LSB_REG … #define DS2780_ACR_MSB_REG … #define DS2780_ACR_LSB_REG … #define DS2780_ACRL_MSB_REG … #define DS2780_ACRL_LSB_REG … #define DS2780_AS_REG … #define DS2780_SFR_REG … #define DS2780_FULL_MSB_REG … #define DS2780_FULL_LSB_REG … #define DS2780_AE_MSB_REG … #define DS2780_AE_LSB_REG … #define DS2780_SE_MSB_REG … #define DS2780_SE_LSB_REG … /* Register 0x1C - 0x1E Reserved */ #define DS2780_EEPROM_REG … #define DS2780_EEPROM_BLOCK0_START … /* Register 0x20 - 0x2F User EEPROM */ #define DS2780_EEPROM_BLOCK0_END … /* Register 0x30 - 0x5F Reserved */ #define DS2780_EEPROM_BLOCK1_START … #define DS2780_CONTROL_REG … #define DS2780_AB_REG … #define DS2780_AC_MSB_REG … #define DS2780_AC_LSB_REG … #define DS2780_VCHG_REG … #define DS2780_IMIN_REG … #define DS2780_VAE_REG … #define DS2780_IAE_REG … #define DS2780_AE_40_REG … #define DS2780_RSNSP_REG … #define DS2780_FULL_40_MSB_REG … #define DS2780_FULL_40_LSB_REG … #define DS2780_FULL_3040_SLOPE_REG … #define DS2780_FULL_2030_SLOPE_REG … #define DS2780_FULL_1020_SLOPE_REG … #define DS2780_FULL_0010_SLOPE_REG … #define DS2780_AE_3040_SLOPE_REG … #define DS2780_AE_2030_SLOPE_REG … #define DS2780_AE_1020_SLOPE_REG … #define DS2780_AE_0010_SLOPE_REG … #define DS2780_SE_3040_SLOPE_REG … #define DS2780_SE_2030_SLOPE_REG … #define DS2780_SE_1020_SLOPE_REG … #define DS2780_SE_0010_SLOPE_REG … #define DS2780_RSGAIN_MSB_REG … #define DS2780_RSGAIN_LSB_REG … #define DS2780_RSTC_REG … #define DS2780_FRSGAIN_MSB_REG … #define DS2780_FRSGAIN_LSB_REG … #define DS2780_EEPROM_BLOCK1_END … /* Register 0x7D - 0xFF Reserved */ /* Number of valid register addresses */ #define DS2780_DATA_SIZE … /* Status register bits */ #define DS2780_STATUS_REG_CHGTF … #define DS2780_STATUS_REG_AEF … #define DS2780_STATUS_REG_SEF … #define DS2780_STATUS_REG_LEARNF … /* Bit 3 Reserved */ #define DS2780_STATUS_REG_UVF … #define DS2780_STATUS_REG_PORF … /* Bit 0 Reserved */ /* Control register bits */ /* Bit 7 Reserved */ #define DS2780_CONTROL_REG_UVEN … #define DS2780_CONTROL_REG_PMOD … #define DS2780_CONTROL_REG_RNAOP … /* Bit 0 - 3 Reserved */ /* Special feature register bits */ /* Bit 1 - 7 Reserved */ #define DS2780_SFR_REG_PIOSC … /* EEPROM register bits */ #define DS2780_EEPROM_REG_EEC … #define DS2780_EEPROM_REG_LOCK … /* Bit 2 - 6 Reserved */ #define DS2780_EEPROM_REG_BL1 … #define DS2780_EEPROM_REG_BL0 … extern int w1_ds2780_io(struct device *dev, char *buf, int addr, size_t count, int io); extern int w1_ds2780_eeprom_cmd(struct device *dev, int addr, int cmd); #endif /* !_W1_DS2780_H */
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