// SPDX-License-Identifier: GPL-2.0+ /* * Watchdog driver for Marvell Armada 37xx SoCs * * Author: Marek Behún <[email protected]> */ #include <linux/clk.h> #include <linux/err.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/types.h> #include <linux/watchdog.h> /* * There are four counters that can be used for watchdog on Armada 37xx. * The addresses for counter control registers are register base plus ID*0x10, * where ID is 0, 1, 2 or 3. * * In this driver we use IDs 0 and 1. Counter ID 1 is used as watchdog counter, * while counter ID 0 is used to implement pinging the watchdog: counter ID 1 is * set to restart counting from initial value on counter ID 0 end count event. * Pinging is done by forcing immediate end count event on counter ID 0. * If only one counter was used, pinging would have to be implemented by * disabling and enabling the counter, leaving the system in a vulnerable state * for a (really) short period of time. * * Counters ID 2 and 3 are enabled by default even before U-Boot loads, * therefore this driver does not provide a way to use them, eg. by setting a * property in device tree. */ #define CNTR_ID_RETRIGGER … #define CNTR_ID_WDOG … /* relative to cpu_misc */ #define WDT_TIMER_SELECT … #define WDT_TIMER_SELECT_MASK … #define WDT_TIMER_SELECT_VAL … /* relative to reg */ #define CNTR_CTRL(id) … #define CNTR_CTRL_ENABLE … #define CNTR_CTRL_ACTIVE … #define CNTR_CTRL_MODE_MASK … #define CNTR_CTRL_MODE_ONESHOT … #define CNTR_CTRL_MODE_HWSIG … #define CNTR_CTRL_TRIG_SRC_MASK … #define CNTR_CTRL_TRIG_SRC_PREV_CNTR … #define CNTR_CTRL_PRESCALE_MASK … #define CNTR_CTRL_PRESCALE_MIN … #define CNTR_CTRL_PRESCALE_SHIFT … #define CNTR_COUNT_LOW(id) … #define CNTR_COUNT_HIGH(id) … #define WATCHDOG_TIMEOUT … static unsigned int timeout; module_param(timeout, int, 0); MODULE_PARM_DESC(…) …; static bool nowayout = … WATCHDOG_NOWAYOUT; module_param(nowayout, bool, 0); MODULE_PARM_DESC(…) …; struct armada_37xx_watchdog { … }; static u64 get_counter_value(struct armada_37xx_watchdog *dev, int id) { … } static void set_counter_value(struct armada_37xx_watchdog *dev, int id, u64 val) { … } static void counter_enable(struct armada_37xx_watchdog *dev, int id) { … } static void counter_disable(struct armada_37xx_watchdog *dev, int id) { … } static void init_counter(struct armada_37xx_watchdog *dev, int id, u32 mode, u32 trig_src) { … } static int armada_37xx_wdt_ping(struct watchdog_device *wdt) { … } static unsigned int armada_37xx_wdt_get_timeleft(struct watchdog_device *wdt) { … } static int armada_37xx_wdt_set_timeout(struct watchdog_device *wdt, unsigned int timeout) { … } static bool armada_37xx_wdt_is_running(struct armada_37xx_watchdog *dev) { … } static int armada_37xx_wdt_start(struct watchdog_device *wdt) { … } static int armada_37xx_wdt_stop(struct watchdog_device *wdt) { … } static const struct watchdog_info armada_37xx_wdt_info = …; static const struct watchdog_ops armada_37xx_wdt_ops = …; static int armada_37xx_wdt_probe(struct platform_device *pdev) { … } static int __maybe_unused armada_37xx_wdt_suspend(struct device *dev) { … } static int __maybe_unused armada_37xx_wdt_resume(struct device *dev) { … } static const struct dev_pm_ops armada_37xx_wdt_dev_pm_ops = …; #ifdef CONFIG_OF static const struct of_device_id armada_37xx_wdt_match[] = …; MODULE_DEVICE_TABLE(of, armada_37xx_wdt_match); #endif static struct platform_driver armada_37xx_wdt_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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