// SPDX-License-Identifier: GPL-2.0+ /* * Cadence WDT driver - Used by Xilinx Zynq * * Copyright (C) 2010 - 2014 Xilinx, Inc. * */ #include <linux/clk.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/watchdog.h> #define CDNS_WDT_DEFAULT_TIMEOUT … /* Supports 1 - 516 sec */ #define CDNS_WDT_MIN_TIMEOUT … #define CDNS_WDT_MAX_TIMEOUT … /* Restart key */ #define CDNS_WDT_RESTART_KEY … /* Counter register access key */ #define CDNS_WDT_REGISTER_ACCESS_KEY … /* Counter value divisor */ #define CDNS_WDT_COUNTER_VALUE_DIVISOR … /* Clock prescaler value and selection */ #define CDNS_WDT_PRESCALE_64 … #define CDNS_WDT_PRESCALE_512 … #define CDNS_WDT_PRESCALE_4096 … #define CDNS_WDT_PRESCALE_SELECT_64 … #define CDNS_WDT_PRESCALE_SELECT_512 … #define CDNS_WDT_PRESCALE_SELECT_4096 … /* Input clock frequency */ #define CDNS_WDT_CLK_10MHZ … #define CDNS_WDT_CLK_75MHZ … /* Counter maximum value */ #define CDNS_WDT_COUNTER_MAX … static int wdt_timeout; static int nowayout = … WATCHDOG_NOWAYOUT; module_param(wdt_timeout, int, 0644); MODULE_PARM_DESC(…) …; module_param(nowayout, int, 0644); MODULE_PARM_DESC(…) …; /** * struct cdns_wdt - Watchdog device structure * @regs: baseaddress of device * @rst: reset flag * @clk: struct clk * of a clock source * @prescaler: for saving prescaler value * @ctrl_clksel: counter clock prescaler selection * @io_lock: spinlock for IO register access * @cdns_wdt_device: watchdog device structure * * Structure containing parameters specific to cadence watchdog. */ struct cdns_wdt { … }; /* Write access to Registers */ static inline void cdns_wdt_writereg(struct cdns_wdt *wdt, u32 offset, u32 val) { … } /*************************Register Map**************************************/ /* Register Offsets for the WDT */ #define CDNS_WDT_ZMR_OFFSET … #define CDNS_WDT_CCR_OFFSET … #define CDNS_WDT_RESTART_OFFSET … #define CDNS_WDT_SR_OFFSET … /* * Zero Mode Register - This register controls how the time out is indicated * and also contains the access code to allow writes to the register (0xABC). */ #define CDNS_WDT_ZMR_WDEN_MASK … #define CDNS_WDT_ZMR_RSTEN_MASK … #define CDNS_WDT_ZMR_IRQEN_MASK … #define CDNS_WDT_ZMR_RSTLEN_16 … #define CDNS_WDT_ZMR_ZKEY_VAL … /* * Counter Control register - This register controls how fast the timer runs * and the reset value and also contains the access code to allow writes to * the register. */ #define CDNS_WDT_CCR_CRV_MASK … /** * cdns_wdt_stop - Stop the watchdog. * * @wdd: watchdog device * * Read the contents of the ZMR register, clear the WDEN bit * in the register and set the access key for successful write. * * Return: always 0 */ static int cdns_wdt_stop(struct watchdog_device *wdd) { … } /** * cdns_wdt_reload - Reload the watchdog timer (i.e. pat the watchdog). * * @wdd: watchdog device * * Write the restart key value (0x00001999) to the restart register. * * Return: always 0 */ static int cdns_wdt_reload(struct watchdog_device *wdd) { … } /** * cdns_wdt_start - Enable and start the watchdog. * * @wdd: watchdog device * * The counter value is calculated according to the formula: * calculated count = (timeout * clock) / prescaler + 1. * The calculated count is divided by 0x1000 to obtain the field value * to write to counter control register. * Clears the contents of prescaler and counter reset value. Sets the * prescaler to 4096 and the calculated count and access key * to write to CCR Register. * Sets the WDT (WDEN bit) and either the Reset signal(RSTEN bit) * or Interrupt signal(IRQEN) with a specified cycles and the access * key to write to ZMR Register. * * Return: always 0 */ static int cdns_wdt_start(struct watchdog_device *wdd) { … } /** * cdns_wdt_settimeout - Set a new timeout value for the watchdog device. * * @wdd: watchdog device * @new_time: new timeout value that needs to be set * Return: 0 on success * * Update the watchdog_device timeout with new value which is used when * cdns_wdt_start is called. */ static int cdns_wdt_settimeout(struct watchdog_device *wdd, unsigned int new_time) { … } /** * cdns_wdt_irq_handler - Notifies of watchdog timeout. * * @irq: interrupt number * @dev_id: pointer to a platform device structure * Return: IRQ_HANDLED * * The handler is invoked when the watchdog times out and a * reset on timeout has not been enabled. */ static irqreturn_t cdns_wdt_irq_handler(int irq, void *dev_id) { … } /* * Info structure used to indicate the features supported by the device * to the upper layers. This is defined in watchdog.h header file. */ static const struct watchdog_info cdns_wdt_info = …; /* Watchdog Core Ops */ static const struct watchdog_ops cdns_wdt_ops = …; /************************Platform Operations*****************************/ /** * cdns_wdt_probe - Probe call for the device. * * @pdev: handle to the platform device structure. * Return: 0 on success, negative error otherwise. * * It does all the memory allocation and registration for the device. */ static int cdns_wdt_probe(struct platform_device *pdev) { … } /** * cdns_wdt_suspend - Stop the device. * * @dev: handle to the device structure. * Return: 0 always. */ static int __maybe_unused cdns_wdt_suspend(struct device *dev) { … } /** * cdns_wdt_resume - Resume the device. * * @dev: handle to the device structure. * Return: 0 on success, errno otherwise. */ static int __maybe_unused cdns_wdt_resume(struct device *dev) { … } static SIMPLE_DEV_PM_OPS(cdns_wdt_pm_ops, cdns_wdt_suspend, cdns_wdt_resume); static const struct of_device_id cdns_wdt_of_match[] = …; MODULE_DEVICE_TABLE(of, cdns_wdt_of_match); /* Driver Structure */ static struct platform_driver cdns_wdt_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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