// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2004 Simtec Electronics * Ben Dooks <[email protected]> * * S3C2410 Watchdog Timer Support * * Based on, softdog.c by Alan Cox, * (c) Copyright 1996 Alan Cox <[email protected]> */ #include <linux/bits.h> #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/types.h> #include <linux/timer.h> #include <linux/watchdog.h> #include <linux/platform_device.h> #include <linux/interrupt.h> #include <linux/clk.h> #include <linux/uaccess.h> #include <linux/io.h> #include <linux/cpufreq.h> #include <linux/slab.h> #include <linux/err.h> #include <linux/of.h> #include <linux/regmap.h> #include <linux/delay.h> #include <linux/soc/samsung/exynos-pmu.h> #define S3C2410_WTCON … #define S3C2410_WTDAT … #define S3C2410_WTCNT … #define S3C2410_WTCLRINT … #define S3C2410_WTCNT_MAXCNT … #define S3C2410_WTCON_RSTEN … #define S3C2410_WTCON_INTEN … #define S3C2410_WTCON_ENABLE … #define S3C2410_WTCON_DBGACK_MASK … #define S3C2410_WTCON_DIV16 … #define S3C2410_WTCON_DIV32 … #define S3C2410_WTCON_DIV64 … #define S3C2410_WTCON_DIV128 … #define S3C2410_WTCON_MAXDIV … #define S3C2410_WTCON_PRESCALE(x) … #define S3C2410_WTCON_PRESCALE_MASK … #define S3C2410_WTCON_PRESCALE_MAX … #define S3C2410_WATCHDOG_ATBOOT … #define S3C2410_WATCHDOG_DEFAULT_TIME … #define EXYNOS5_RST_STAT_REG_OFFSET … #define EXYNOS5_WDT_DISABLE_REG_OFFSET … #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET … #define EXYNOS850_CLUSTER0_NONCPU_OUT … #define EXYNOS850_CLUSTER0_NONCPU_INT_EN … #define EXYNOS850_CLUSTER1_NONCPU_OUT … #define EXYNOS850_CLUSTER1_NONCPU_INT_EN … #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT … #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN … #define EXYNOS850_CLUSTER0_WDTRESET_BIT … #define EXYNOS850_CLUSTER1_WDTRESET_BIT … #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT … #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT … #define GS_CLUSTER0_NONCPU_OUT … #define GS_CLUSTER1_NONCPU_OUT … #define GS_CLUSTER0_NONCPU_INT_EN … #define GS_CLUSTER1_NONCPU_INT_EN … #define GS_CLUSTER2_NONCPU_INT_EN … #define GS_RST_STAT_REG_OFFSET … /** * DOC: Quirk flags for different Samsung watchdog IP-cores * * This driver supports multiple Samsung SoCs, each of which might have * different set of registers and features supported. As watchdog block * sometimes requires modifying PMU registers for proper functioning, register * differences in both watchdog and PMU IP-cores should be accounted for. Quirk * flags described below serve the purpose of telling the driver about mentioned * SoC traits, and can be specified in driver data for each particular supported * device. * * %QUIRK_HAS_WTCLRINT_REG: Watchdog block has WTCLRINT register. It's used to * clear the interrupt once the interrupt service routine is complete. It's * write-only, writing any values to this register clears the interrupt, but * reading is not permitted. * * %QUIRK_HAS_PMU_MASK_RESET: PMU block has the register for disabling/enabling * WDT reset request. On old SoCs it's usually called MASK_WDT_RESET_REQUEST, * new SoCs have CLUSTERx_NONCPU_INT_EN register, which 'mask_bit' value is * inverted compared to the former one. * * %QUIRK_HAS_PMU_RST_STAT: PMU block has RST_STAT (reset status) register, * which contains bits indicating the reason for most recent CPU reset. If * present, driver will use this register to check if previous reboot was due to * watchdog timer reset. * * %QUIRK_HAS_PMU_AUTO_DISABLE: PMU block has AUTOMATIC_WDT_RESET_DISABLE * register. If 'mask_bit' bit is set, PMU will disable WDT reset when * corresponding processor is in reset state. * * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) * with "watchdog counter enable" bit. That bit should be set to make watchdog * counter running. * * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. * Debug mode is determined by the DBGACK CPU signal. */ #define QUIRK_HAS_WTCLRINT_REG … #define QUIRK_HAS_PMU_MASK_RESET … #define QUIRK_HAS_PMU_RST_STAT … #define QUIRK_HAS_PMU_AUTO_DISABLE … #define QUIRK_HAS_PMU_CNT_EN … #define QUIRK_HAS_DBGACK_BIT … /* These quirks require that we have a PMU register map */ #define QUIRKS_HAVE_PMUREG … static bool nowayout = … WATCHDOG_NOWAYOUT; static int tmr_margin; static int tmr_atboot = …; static int soft_noboot; module_param(tmr_margin, int, 0); module_param(tmr_atboot, int, 0); module_param(nowayout, bool, 0); module_param(soft_noboot, int, 0); MODULE_PARM_DESC(…) …; MODULE_PARM_DESC(…) …; MODULE_PARM_DESC(…) …; MODULE_PARM_DESC(…) …; /** * struct s3c2410_wdt_variant - Per-variant config data * * @disable_reg: Offset in pmureg for the register that disables the watchdog * timer reset functionality. * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog * timer reset functionality. * @mask_reset_inv: If set, mask_reset_reg value will have inverted meaning. * @mask_bit: Bit number for the watchdog timer in the disable register and the * mask reset register. * @rst_stat_reg: Offset in pmureg for the register that has the reset status. * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog * reset. * @cnt_en_reg: Offset in pmureg for the register that enables WDT counter. * @cnt_en_bit: Bit number for "watchdog counter enable" in cnt_en register. * @quirks: A bitfield of quirks. */ struct s3c2410_wdt_variant { … }; struct s3c2410_wdt { … }; static const struct s3c2410_wdt_variant drv_data_s3c2410 = …; #ifdef CONFIG_OF static const struct s3c2410_wdt_variant drv_data_s3c6410 = …; static const struct s3c2410_wdt_variant drv_data_exynos5250 = …; static const struct s3c2410_wdt_variant drv_data_exynos5420 = …; static const struct s3c2410_wdt_variant drv_data_exynos7 = …; static const struct s3c2410_wdt_variant drv_data_exynos850_cl0 = …; static const struct s3c2410_wdt_variant drv_data_exynos850_cl1 = …; static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl0 = …; static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = …; static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = …; static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = …; static const struct of_device_id s3c2410_wdt_match[] = …; MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); #endif static const struct platform_device_id s3c2410_wdt_ids[] = …; MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); /* functions */ static inline unsigned long s3c2410wdt_get_freq(struct s3c2410_wdt *wdt) { … } static inline unsigned int s3c2410wdt_max_timeout(struct s3c2410_wdt *wdt) { … } static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask) { … } static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) { … } static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en) { … } static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) { … } /* Disable watchdog outputs if CPU is in debug mode */ static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt) { … } static int s3c2410wdt_keepalive(struct watchdog_device *wdd) { … } static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) { … } static int s3c2410wdt_stop(struct watchdog_device *wdd) { … } static int s3c2410wdt_start(struct watchdog_device *wdd) { … } static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned int timeout) { … } static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action, void *data) { … } #define OPTIONS … static const struct watchdog_info s3c2410_wdt_ident = …; static const struct watchdog_ops s3c2410wdt_ops = …; static const struct watchdog_device s3c2410_wdd = …; /* interrupt handler code */ static irqreturn_t s3c2410wdt_irq(int irqno, void *param) { … } static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) { … } static inline int s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) { … } static void s3c2410wdt_wdt_disable_action(void *data) { … } static int s3c2410wdt_probe(struct platform_device *pdev) { … } static void s3c2410wdt_shutdown(struct platform_device *dev) { … } static int s3c2410wdt_suspend(struct device *dev) { … } static int s3c2410wdt_resume(struct device *dev) { … } static DEFINE_SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend, s3c2410wdt_resume); static struct platform_driver s3c2410wdt_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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