/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ /* * Copyright (c) 2022 MediaTek Inc. * Author: Sam Shih <[email protected]> */ #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986 #define _DT_BINDINGS_RESET_CONTROLLER_MT7986 /* INFRACFG resets */ #define MT7986_INFRACFG_PEXTP_MAC_SW_RST … #define MT7986_INFRACFG_SSUSB_SW_RST … #define MT7986_INFRACFG_EIP97_SW_RST … #define MT7986_INFRACFG_AUDIO_SW_RST … #define MT7986_INFRACFG_CQ_DMA_SW_RST … #define MT7986_INFRACFG_TRNG_SW_RST … #define MT7986_INFRACFG_AP_DMA_SW_RST … #define MT7986_INFRACFG_I2C_SW_RST … #define MT7986_INFRACFG_NFI_SW_RST … #define MT7986_INFRACFG_SPI0_SW_RST … #define MT7986_INFRACFG_SPI1_SW_RST … #define MT7986_INFRACFG_UART0_SW_RST … #define MT7986_INFRACFG_UART1_SW_RST … #define MT7986_INFRACFG_UART2_SW_RST … #define MT7986_INFRACFG_AUXADC_SW_RST … #define MT7986_INFRACFG_APXGPT_SW_RST … #define MT7986_INFRACFG_PWM_SW_RST … #define MT7986_INFRACFG_SW_RST_NUM … /* TOPRGU resets */ #define MT7986_TOPRGU_APMIXEDSYS_SW_RST … #define MT7986_TOPRGU_SGMII0_SW_RST … #define MT7986_TOPRGU_SGMII1_SW_RST … #define MT7986_TOPRGU_INFRA_SW_RST … #define MT7986_TOPRGU_U2PHY_SW_RST … #define MT7986_TOPRGU_PCIE_SW_RST … #define MT7986_TOPRGU_SSUSB_SW_RST … #define MT7986_TOPRGU_ETHDMA_SW_RST … #define MT7986_TOPRGU_CONSYS_SW_RST … #define MT7986_TOPRGU_SW_RST_NUM … /* ETHSYS Subsystem resets */ #define MT7986_ETHSYS_FE_SW_RST … #define MT7986_ETHSYS_PMTR_SW_RST … #define MT7986_ETHSYS_GMAC_SW_RST … #define MT7986_ETHSYS_PPE0_SW_RST … #define MT7986_ETHSYS_PPE1_SW_RST … #define MT7986_ETHSYS_SW_RST_NUM … #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */
Codebase Browser
linux