linux/drivers/watchdog/marvell_gti_wdt.c

// SPDX-License-Identifier: GPL-2.0
/* Marvell GTI Watchdog driver
 *
 * Copyright (C) 2023 Marvell.
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/watchdog.h>

/*
 * Hardware supports following mode of operation:
 * 1) Interrupt Only:
 *    This will generate the interrupt to arm core whenever timeout happens.
 *
 * 2) Interrupt + del3t (Interrupt to firmware (SCP processor)).
 *    This will generate interrupt to arm core on 1st timeout happens
 *    This will generate interrupt to SCP processor on 2nd timeout happens
 *
 * 3) Interrupt + Interrupt to SCP processor (called delt3t) + reboot.
 *    This will generate interrupt to arm core on 1st timeout happens
 *    Will generate interrupt to SCP processor on 2nd timeout happens,
 *    if interrupt is configured.
 *    Reboot on 3rd timeout.
 *
 * Driver will use hardware in mode-3 above so that system can reboot in case
 * a hardware hang. Also h/w is configured not to generate SCP interrupt, so
 * effectively 2nd timeout is ignored within hardware.
 *
 * First timeout is effectively watchdog pretimeout.
 */

/* GTI CWD Watchdog (GTI_CWD_WDOG) Register */
#define GTI_CWD_WDOG(reg_offset)
#define GTI_CWD_WDOG_MODE_INT_DEL3T_RST
#define GTI_CWD_WDOG_MODE_MASK
#define GTI_CWD_WDOG_LEN_SHIFT
#define GTI_CWD_WDOG_LEN_MASK
#define GTI_CWD_WDOG_CNT_SHIFT
#define GTI_CWD_WDOG_CNT_MASK

/* GTI CWD Watchdog Interrupt (GTI_CWD_INT) Register */
#define GTI_CWD_INT
#define GTI_CWD_INT_PENDING_STATUS(bit)

/* GTI CWD Watchdog Interrupt Enable Clear (GTI_CWD_INT_ENA_CLR) Register */
#define GTI_CWD_INT_ENA_CLR
#define GTI_CWD_INT_ENA_CLR_VAL(bit)

/* GTI CWD Watchdog Interrupt Enable Set (GTI_CWD_INT_ENA_SET) Register */
#define GTI_CWD_INT_ENA_SET
#define GTI_CWD_INT_ENA_SET_VAL(bit)

/* GTI CWD Watchdog Poke (GTI_CWD_POKE) Registers */
#define GTI_CWD_POKE(reg_offset)
#define GTI_CWD_POKE_VAL

struct gti_match_data {};

static const struct gti_match_data match_data_octeontx2 =;

static const struct gti_match_data match_data_cn10k =;

struct gti_wdt_priv {};

static irqreturn_t gti_wdt_interrupt(int irq, void *data)
{}

static int gti_wdt_ping(struct watchdog_device *wdev)
{}

static int gti_wdt_start(struct watchdog_device *wdev)
{}

static int gti_wdt_stop(struct watchdog_device *wdev)
{}

static int gti_wdt_settimeout(struct watchdog_device *wdev,
					unsigned int timeout)
{}

static int gti_wdt_set_pretimeout(struct watchdog_device *wdev,
					unsigned int timeout)
{}

static void gti_clk_disable_unprepare(void *data)
{}

static int gti_wdt_get_cntfrq(struct platform_device *pdev,
			      struct gti_wdt_priv *priv)
{}

static const struct watchdog_info gti_wdt_ident =;

static const struct watchdog_ops gti_wdt_ops =;

static int gti_wdt_probe(struct platform_device *pdev)
{}

static const struct of_device_id gti_wdt_of_match[] =;
MODULE_DEVICE_TABLE(of, gti_wdt_of_match);

static struct platform_driver gti_wdt_driver =;
module_platform_driver();

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();