// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2016 IBM Corporation * * Joel Stanley <[email protected]> */ #include <linux/bits.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/kstrtox.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/watchdog.h> static bool nowayout = … WATCHDOG_NOWAYOUT; module_param(nowayout, bool, 0); MODULE_PARM_DESC(…) …; struct aspeed_wdt_config { … }; struct aspeed_wdt { … }; static const struct aspeed_wdt_config ast2400_config = …; static const struct aspeed_wdt_config ast2500_config = …; static const struct aspeed_wdt_config ast2600_config = …; static const struct of_device_id aspeed_wdt_of_table[] = …; MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); #define WDT_STATUS … #define WDT_RELOAD_VALUE … #define WDT_RESTART … #define WDT_CTRL … #define WDT_CTRL_BOOT_SECONDARY … #define WDT_CTRL_RESET_MODE_SOC … #define WDT_CTRL_RESET_MODE_FULL_CHIP … #define WDT_CTRL_RESET_MODE_ARM_CPU … #define WDT_CTRL_1MHZ_CLK … #define WDT_CTRL_WDT_EXT … #define WDT_CTRL_WDT_INTR … #define WDT_CTRL_RESET_SYSTEM … #define WDT_CTRL_ENABLE … #define WDT_TIMEOUT_STATUS … #define WDT_TIMEOUT_STATUS_IRQ … #define WDT_TIMEOUT_STATUS_BOOT_SECONDARY … #define WDT_CLEAR_TIMEOUT_STATUS … #define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION … #define WDT_RESET_MASK1 … #define WDT_RESET_MASK2 … /* * WDT_RESET_WIDTH controls the characteristics of the external pulse (if * enabled), specifically: * * * Pulse duration * * Drive mode: push-pull vs open-drain * * Polarity: Active high or active low * * Pulse duration configuration is available on both the AST2400 and AST2500, * though the field changes between SoCs: * * AST2400: Bits 7:0 * AST2500: Bits 19:0 * * This difference is captured in struct aspeed_wdt_config. * * The AST2500 exposes the drive mode and polarity options, but not in a * regular fashion. For read purposes, bit 31 represents active high or low, * and bit 30 represents push-pull or open-drain. With respect to write, magic * values need to be written to the top byte to change the state of the drive * mode and polarity bits. Any other value written to the top byte has no * effect on the state of the drive mode or polarity bits. However, the pulse * width value must be preserved (as desired) if written. */ #define WDT_RESET_WIDTH … #define WDT_RESET_WIDTH_ACTIVE_HIGH … #define WDT_ACTIVE_HIGH_MAGIC … #define WDT_ACTIVE_LOW_MAGIC … #define WDT_RESET_WIDTH_PUSH_PULL … #define WDT_PUSH_PULL_MAGIC … #define WDT_OPEN_DRAIN_MAGIC … #define WDT_RESTART_MAGIC … /* 32 bits at 1MHz, in milliseconds */ #define WDT_MAX_TIMEOUT_MS … #define WDT_DEFAULT_TIMEOUT … #define WDT_RATE_1MHZ … static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd) { … } static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count) { … } static int aspeed_wdt_start(struct watchdog_device *wdd) { … } static int aspeed_wdt_stop(struct watchdog_device *wdd) { … } static int aspeed_wdt_ping(struct watchdog_device *wdd) { … } static int aspeed_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout) { … } static int aspeed_wdt_set_pretimeout(struct watchdog_device *wdd, unsigned int pretimeout) { … } static int aspeed_wdt_restart(struct watchdog_device *wdd, unsigned long action, void *data) { … } /* access_cs0 shows if cs0 is accessible, hence the reverted bit */ static ssize_t access_cs0_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t access_cs0_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) { … } /* * This attribute exists only if the system has booted from the alternate * flash with 'alt-boot' option. * * At alternate flash the 'access_cs0' sysfs node provides: * ast2400: a way to get access to the primary SPI flash chip at CS0 * after booting from the alternate chip at CS1. * ast2500: a way to restore the normal address mapping from * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1). * * Clearing the boot code selection and timeout counter also resets to the * initial state the chip select line mapping. When the SoC is in normal * mapping state (i.e. booted from CS0), clearing those bits does nothing for * both versions of the SoC. For alternate boot mode (booted from CS1 due to * wdt2 expiration) the behavior differs as described above. * * This option can be used with wdt2 (watchdog1) only. */ static DEVICE_ATTR_RW(access_cs0); static struct attribute *bswitch_attrs[] = …; ATTRIBUTE_GROUPS(…); static const struct watchdog_ops aspeed_wdt_ops = …; static const struct watchdog_info aspeed_wdt_info = …; static const struct watchdog_info aspeed_wdt_pretimeout_info = …; static irqreturn_t aspeed_wdt_irq(int irq, void *arg) { … } static int aspeed_wdt_probe(struct platform_device *pdev) { … } static struct platform_driver aspeed_watchdog_driver = …; static int __init aspeed_wdt_init(void) { … } arch_initcall(aspeed_wdt_init); static void __exit aspeed_wdt_exit(void) { … } module_exit(aspeed_wdt_exit); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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