/* SPDX-License-Identifier: GPL-2.0 */ /* * sp5100_tco: TCO timer driver for sp5100 chipsets. * * (c) Copyright 2009 Google Inc., All Rights Reserved. * * TCO timer driver for sp5100 chipsets */ #include <linux/bitops.h> /* * Some address definitions for the Watchdog */ #define SP5100_WDT_MEM_MAP_SIZE … #define SP5100_WDT_CONTROL(base) … #define SP5100_WDT_COUNT(base) … #define SP5100_WDT_START_STOP_BIT … #define SP5100_WDT_FIRED … #define SP5100_WDT_ACTION_RESET … #define SP5100_WDT_DISABLED … #define SP5100_WDT_TRIGGER_BIT … #define SP5100_PM_IOPORTS_SIZE … /* * These two IO registers are hardcoded and there doesn't seem to be a way to * read them from a register. */ /* For SP5100/SB7x0/SB8x0 chipset */ #define SP5100_IO_PM_INDEX_REG … #define SP5100_IO_PM_DATA_REG … /* For SP5100/SB7x0 chipset */ #define SP5100_SB_RESOURCE_MMIO_BASE … #define SP5100_PM_WATCHDOG_CONTROL … #define SP5100_PM_WATCHDOG_BASE … #define SP5100_PCI_WATCHDOG_MISC_REG … #define SP5100_PCI_WATCHDOG_DECODE_EN … #define SP5100_PM_WATCHDOG_DISABLE … #define SP5100_PM_WATCHDOG_SECOND_RES … #define SP5100_DEVNAME … /* For SB8x0(or later) chipset */ #define SB800_PM_ACPI_MMIO_EN … #define SB800_PM_WATCHDOG_CONTROL … #define SB800_PM_WATCHDOG_BASE … #define SB800_PM_WATCHDOG_CONFIG … #define SB800_PCI_WATCHDOG_DECODE_EN … #define SB800_PM_WATCHDOG_DISABLE … #define SB800_PM_WATCHDOG_SECOND_RES … #define SB800_ACPI_MMIO_DECODE_EN … #define SB800_ACPI_MMIO_SEL … #define SB800_ACPI_MMIO_MASK … #define SB800_PM_WDT_MMIO_OFFSET … #define SB800_DEVNAME … /* For recent chips with embedded FCH (rev 40+) */ #define EFCH_PM_DECODEEN … #define EFCH_PM_DECODEEN_WDT_TMREN … #define EFCH_PM_DECODEEN3 … #define EFCH_PM_DECODEEN_SECOND_RES … #define EFCH_PM_WATCHDOG_DISABLE … /* WDT MMIO if enabled with PM00_DECODEEN_WDT_TMREN */ #define EFCH_PM_WDT_ADDR … #define EFCH_PM_ISACONTROL … #define EFCH_PM_ISACONTROL_MMIOEN … #define EFCH_PM_ACPI_MMIO_ADDR … #define EFCH_PM_ACPI_MMIO_PM_OFFSET … #define EFCH_PM_ACPI_MMIO_WDT_OFFSET … #define EFCH_PM_ACPI_MMIO_PM_ADDR … #define EFCH_PM_ACPI_MMIO_PM_SIZE … #define AMD_ZEN_SMBUS_PCI_REV …
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