/* SPDX-License-Identifier: GPL-2.0+ */ /* * nv_tco: TCO timer driver for nVidia chipsets. * * (c) Copyright 2005 Google Inc., All Rights Reserved. * * Supported Chipsets: * - MCP51/MCP55 * * (c) Copyright 2000 kernel concepts <[email protected]>, All Rights * Reserved. * https://www.kernelconcepts.de * * Neither kernel concepts nor Nils Faerber admit liability nor provide * warranty for any of this software. This material is provided * "AS-IS" and at no charge. * * (c) Copyright 2000 kernel concepts <[email protected]> * developed for * Jentro AG, Haar/Munich (Germany) * * TCO timer driver for NV chipsets * based on softdog.c by Alan Cox <[email protected]> */ /* * Some address definitions for the TCO */ #define TCO_RLD(base) … #define TCO_TMR(base) … #define TCO_STS(base) … /* * TCO Boot Status bit: set on TCO reset, reset by software or standby * power-good (survives reboots), unfortunately this bit is never * set. */ #define TCO_STS_BOOT_STS … /* * first and 2nd timeout status bits, these also survive a warm boot, * and they work, so we use them. */ #define TCO_STS_TCO_INT_STS … #define TCO_STS_TCO2TO_STS … #define TCO_STS_RESET … #define TCO_CNT(base) … #define TCO_CNT_TCOHALT … #define MCP51_SMBUS_SETUP_B … #define MCP51_SMBUS_SETUP_B_TCO_REBOOT … /* * The SMI_EN register is at the base io address + 0x04, * while TCOBASE is + 0x40. */ #define MCP51_SMI_EN(base) … #define MCP51_SMI_EN_TCO …
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