// SPDX-License-Identifier: GPL-2.0-only /* * Realtek Otto MIPS platform watchdog * * Watchdog timer that will reset the system after timeout, using the selected * reset mode. * * Counter scaling and timeouts: * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8} * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0 * Generates an interrupt, WDT cannot be stopped after phase 1 * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0 * Resets the system according to RST_MODE */ #include <linux/bits.h> #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/math.h> #include <linux/minmax.h> #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/reboot.h> #include <linux/watchdog.h> #define OTTO_WDT_REG_CNTR … #define OTTO_WDT_CNTR_PING … #define OTTO_WDT_REG_INTR … #define OTTO_WDT_INTR_PHASE_1 … #define OTTO_WDT_INTR_PHASE_2 … #define OTTO_WDT_REG_CTRL … #define OTTO_WDT_CTRL_ENABLE … #define OTTO_WDT_CTRL_PRESCALE … #define OTTO_WDT_CTRL_PHASE1 … #define OTTO_WDT_CTRL_PHASE2 … #define OTTO_WDT_CTRL_RST_MODE … #define OTTO_WDT_MODE_SOC … #define OTTO_WDT_MODE_CPU … #define OTTO_WDT_MODE_SOFTWARE … #define OTTO_WDT_CTRL_DEFAULT … #define OTTO_WDT_PRESCALE_MAX … /* * One higher than the max values contained in PHASE{1,2}, since a value of 0 * corresponds to one tick. */ #define OTTO_WDT_PHASE_TICKS_MAX … /* * The maximum reset delay is actually 2×32 ticks, but that would require large * pretimeout values for timeouts longer than 32 ticks. Limit the maximum timeout * to 32 + 1 to ensure small pretimeout values can be configured as expected. */ #define OTTO_WDT_TIMEOUT_TICKS_MAX … struct otto_wdt_ctrl { … }; static int otto_wdt_start(struct watchdog_device *wdev) { … } static int otto_wdt_stop(struct watchdog_device *wdev) { … } static int otto_wdt_ping(struct watchdog_device *wdev) { … } static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale) { … } /* * The timer asserts the PHASE1/PHASE2 IRQs when the number of ticks exceeds * the value stored in those fields. This means each phase will run for at least * one tick, so small values need to be clamped to correctly reflect the timeout. */ static inline unsigned int div_round_ticks(unsigned int val, unsigned int tick_duration, unsigned int min_ticks) { … } static int otto_wdt_determine_timeouts(struct watchdog_device *wdev, unsigned int timeout, unsigned int pretimeout) { … } static int otto_wdt_set_timeout(struct watchdog_device *wdev, unsigned int val) { … } static int otto_wdt_set_pretimeout(struct watchdog_device *wdev, unsigned int val) { … } static int otto_wdt_restart(struct watchdog_device *wdev, unsigned long reboot_mode, void *data) { … } static irqreturn_t otto_wdt_phase1_isr(int irq, void *dev_id) { … } static const struct watchdog_ops otto_wdt_ops = …; static const struct watchdog_info otto_wdt_info = …; static int otto_wdt_probe_clk(struct otto_wdt_ctrl *ctrl) { … } static int otto_wdt_probe_reset_mode(struct otto_wdt_ctrl *ctrl) { … } static int otto_wdt_probe(struct platform_device *pdev) { … } static const struct of_device_id otto_wdt_ids[] = …; MODULE_DEVICE_TABLE(of, otto_wdt_ids); static struct platform_driver otto_wdt_driver = …; module_platform_driver(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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