linux/drivers/clk/bcm/clk-iproc.h

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (C) 2014 Broadcom Corporation */

#ifndef _CLK_IPROC_H
#define _CLK_IPROC_H

#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/clk-provider.h>

#define IPROC_CLK_NAME_LEN …
#define IPROC_CLK_INVALID_OFFSET …
#define bit_mask(width) …

/* clocks that should not be disabled at runtime */
#define IPROC_CLK_AON …

/* PLL that requires gating through ASIU */
#define IPROC_CLK_PLL_ASIU …

/* PLL that has fractional part of the NDIV */
#define IPROC_CLK_PLL_HAS_NDIV_FRAC …

/*
 * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
 * of the same register following the write to flush the write transaction into
 * the intended register
 */
#define IPROC_CLK_NEEDS_READ_BACK …

/*
 * Some PLLs require the PLL SW override bit to be set before changes can be
 * applied to the PLL
 */
#define IPROC_CLK_PLL_NEEDS_SW_CFG …

/*
 * Some PLLs use a different way to control clock power, via the PWRDWN bit in
 * the PLL control register
 */
#define IPROC_CLK_EMBED_PWRCTRL …

/*
 * Some PLLs have separate registers for Status and Control.  Identify this to
 * let the driver know if additional registers need to be used
 */
#define IPROC_CLK_PLL_SPLIT_STAT_CTRL …

/*
 * Some PLLs have an additional divide by 2 in master clock calculation;
 * MCLK = VCO_freq / (Mdiv * 2). Identify this to let the driver know
 * of modified calculations
 */
#define IPROC_CLK_MCLK_DIV_BY_2 …

/*
 * Some PLLs provide a look up table for the leaf clock frequencies and
 * auto calculates VCO frequency parameters based on the provided leaf
 * clock frequencies. They have a user mode that allows the divider
 * controls to be determined by the user
 */
#define IPROC_CLK_PLL_USER_MODE_ON …

/*
 * Some PLLs have an active low reset
 */
#define IPROC_CLK_PLL_RESET_ACTIVE_LOW …

/*
 * Calculate the PLL parameters are runtime, instead of using table
 */
#define IPROC_CLK_PLL_CALC_PARAM …

/*
 * Parameters for VCO frequency configuration
 *
 * VCO frequency =
 * ((ndiv_int + ndiv_frac / 2^20) * (ref frequency  / pdiv)
 */
struct iproc_pll_vco_param { … };

struct iproc_clk_reg_op { … };

/*
 * Clock gating control at the top ASIU level
 */
struct iproc_asiu_gate { … };

/*
 * Control of powering on/off of a PLL
 *
 * Before powering off a PLL, input isolation (ISO) needs to be enabled
 */
struct iproc_pll_aon_pwr_ctrl { … };

/*
 * Control of the PLL reset
 */
struct iproc_pll_reset_ctrl { … };

/*
 * Control of the Ki, Kp, and Ka parameters
 */
struct iproc_pll_dig_filter_ctrl { … };

/*
 * To enable SW control of the PLL
 */
struct iproc_pll_sw_ctrl { … };

struct iproc_pll_vco_ctrl { … };

/*
 * Main PLL control parameters
 */
struct iproc_pll_ctrl { … };

/*
 * Controls enabling/disabling a PLL derived clock
 */
struct iproc_clk_enable_ctrl { … };

/*
 * Main clock control parameters for clocks derived from the PLLs
 */
struct iproc_clk_ctrl { … };

/*
 * Divisor of the ASIU clocks
 */
struct iproc_asiu_div { … };

void iproc_armpll_setup(struct device_node *node);
void iproc_pll_clk_setup(struct device_node *node,
			 const struct iproc_pll_ctrl *pll_ctrl,
			 const struct iproc_pll_vco_param *vco,
			 unsigned int num_vco_entries,
			 const struct iproc_clk_ctrl *clk_ctrl,
			 unsigned int num_clks);
void iproc_asiu_setup(struct device_node *node,
		      const struct iproc_asiu_div *div,
		      const struct iproc_asiu_gate *gate,
		      unsigned int num_clks);

#endif /* _CLK_IPROC_H */