/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * specific defines for CCD's HFC 2BDS0 PCI chips * * Author Werner Cornelius ([email protected]) * * Copyright 1999 by Werner Cornelius ([email protected]) */ /* * thresholds for transparent B-channel mode * change mask and threshold simultaneously */ #define HFCPCI_BTRANS_THRESHOLD … #define HFCPCI_FILLEMPTY … #define HFCPCI_BTRANS_THRESMASK … /* defines for PCI config */ #define PCI_ENA_MEMIO … #define PCI_ENA_MASTER … /* GCI/IOM bus monitor registers */ #define HCFPCI_C_I … #define HFCPCI_TRxR … #define HFCPCI_MON1_D … #define HFCPCI_MON2_D … /* GCI/IOM bus timeslot registers */ #define HFCPCI_B1_SSL … #define HFCPCI_B2_SSL … #define HFCPCI_AUX1_SSL … #define HFCPCI_AUX2_SSL … #define HFCPCI_B1_RSL … #define HFCPCI_B2_RSL … #define HFCPCI_AUX1_RSL … #define HFCPCI_AUX2_RSL … /* GCI/IOM bus data registers */ #define HFCPCI_B1_D … #define HFCPCI_B2_D … #define HFCPCI_AUX1_D … #define HFCPCI_AUX2_D … /* GCI/IOM bus configuration registers */ #define HFCPCI_MST_EMOD … #define HFCPCI_MST_MODE … #define HFCPCI_CONNECT … /* Interrupt and status registers */ #define HFCPCI_FIFO_EN … #define HFCPCI_TRM … #define HFCPCI_B_MODE … #define HFCPCI_CHIP_ID … #define HFCPCI_CIRM … #define HFCPCI_CTMT … #define HFCPCI_INT_M1 … #define HFCPCI_INT_M2 … #define HFCPCI_INT_S1 … #define HFCPCI_INT_S2 … #define HFCPCI_STATUS … /* S/T section registers */ #define HFCPCI_STATES … #define HFCPCI_SCTRL … #define HFCPCI_SCTRL_E … #define HFCPCI_SCTRL_R … #define HFCPCI_SQ … #define HFCPCI_CLKDEL … #define HFCPCI_B1_REC … #define HFCPCI_B1_SEND … #define HFCPCI_B2_REC … #define HFCPCI_B2_SEND … #define HFCPCI_D_REC … #define HFCPCI_D_SEND … #define HFCPCI_E_REC … /* bits in status register (READ) */ #define HFCPCI_PCI_PROC … #define HFCPCI_NBUSY … #define HFCPCI_TIMER_ELAP … #define HFCPCI_STATINT … #define HFCPCI_FRAMEINT … #define HFCPCI_ANYINT … /* bits in CTMT (Write) */ #define HFCPCI_CLTIMER … #define HFCPCI_TIM3_125 … #define HFCPCI_TIM25 … #define HFCPCI_TIM50 … #define HFCPCI_TIM400 … #define HFCPCI_TIM800 … #define HFCPCI_AUTO_TIMER … #define HFCPCI_TRANSB2 … #define HFCPCI_TRANSB1 … /* bits in CIRM (Write) */ #define HFCPCI_AUX_MSK … #define HFCPCI_RESET … #define HFCPCI_B1_REV … #define HFCPCI_B2_REV … /* bits in INT_M1 and INT_S1 */ #define HFCPCI_INTS_B1TRANS … #define HFCPCI_INTS_B2TRANS … #define HFCPCI_INTS_DTRANS … #define HFCPCI_INTS_B1REC … #define HFCPCI_INTS_B2REC … #define HFCPCI_INTS_DREC … #define HFCPCI_INTS_L1STATE … #define HFCPCI_INTS_TIMER … /* bits in INT_M2 */ #define HFCPCI_PROC_TRANS … #define HFCPCI_GCI_I_CHG … #define HFCPCI_GCI_MON_REC … #define HFCPCI_IRQ_ENABLE … #define HFCPCI_PMESEL … /* bits in STATES */ #define HFCPCI_STATE_MSK … #define HFCPCI_LOAD_STATE … #define HFCPCI_ACTIVATE … #define HFCPCI_DO_ACTION … #define HFCPCI_NT_G2_G3 … /* bits in HFCD_MST_MODE */ #define HFCPCI_MASTER … #define HFCPCI_SLAVE … #define HFCPCI_F0IO_POSITIV … #define HFCPCI_F0_NEGATIV … #define HFCPCI_F0_2C4 … /* remaining bits are for codecs control */ /* bits in HFCD_SCTRL */ #define SCTRL_B1_ENA … #define SCTRL_B2_ENA … #define SCTRL_MODE_TE … #define SCTRL_MODE_NT … #define SCTRL_LOW_PRIO … #define SCTRL_SQ_ENA … #define SCTRL_TEST … #define SCTRL_NONE_CAP … #define SCTRL_PWR_DOWN … /* bits in SCTRL_E */ #define HFCPCI_AUTO_AWAKE … #define HFCPCI_DBIT_1 … #define HFCPCI_IGNORE_COL … #define HFCPCI_CHG_B1_B2 … /* bits in FIFO_EN register */ #define HFCPCI_FIFOEN_B1 … #define HFCPCI_FIFOEN_B2 … #define HFCPCI_FIFOEN_DTX … #define HFCPCI_FIFOEN_B1TX … #define HFCPCI_FIFOEN_B1RX … #define HFCPCI_FIFOEN_B2TX … #define HFCPCI_FIFOEN_B2RX … /* definitions of fifo memory area */ #define MAX_D_FRAMES … #define MAX_B_FRAMES … #define B_SUB_VAL … #define B_FIFO_SIZE … #define D_FIFO_SIZE … #define D_FREG_MASK … struct zt { … }; struct dfifo { … }; struct bzfifo { … }; fifo_area; #define Write_hfc(a, b, c) … #define Read_hfc(a, b) …
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