// SPDX-License-Identifier: GPL-2.0-only // Copyright (C) 2014 Broadcom Corporation #include <linux/kernel.h> #include <linux/slab.h> #include <linux/err.h> #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/of.h> #include <linux/clkdev.h> #include <linux/of_address.h> #include "clk-iproc.h" #define IPROC_CLK_MAX_FREQ_POLICY … #define IPROC_CLK_POLICY_FREQ_OFFSET … #define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT … #define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK … #define IPROC_CLK_PLLARMA_OFFSET … #define IPROC_CLK_PLLARMA_LOCK_SHIFT … #define IPROC_CLK_PLLARMA_PDIV_SHIFT … #define IPROC_CLK_PLLARMA_PDIV_MASK … #define IPROC_CLK_PLLARMA_NDIV_INT_SHIFT … #define IPROC_CLK_PLLARMA_NDIV_INT_MASK … #define IPROC_CLK_PLLARMB_OFFSET … #define IPROC_CLK_PLLARMB_NDIV_FRAC_MASK … #define IPROC_CLK_PLLARMC_OFFSET … #define IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT … #define IPROC_CLK_PLLARMC_MDIV_MASK … #define IPROC_CLK_PLLARMCTL5_OFFSET … #define IPROC_CLK_PLLARMCTL5_H_MDIV_MASK … #define IPROC_CLK_PLLARM_OFFSET_OFFSET … #define IPROC_CLK_PLLARM_SW_CTL_SHIFT … #define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT … #define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK … #define IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK … #define IPROC_CLK_ARM_DIV_OFFSET … #define IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT … #define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK … #define IPROC_CLK_POLICY_DBG_OFFSET … #define IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT … #define IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK … enum iproc_arm_pll_fid { … }; struct iproc_arm_pll { … }; #define to_iproc_arm_pll(hw) … static unsigned int __get_fid(struct iproc_arm_pll *pll) { … } /* * Determine the mdiv (post divider) based on the frequency ID being used. * There are 4 sources that can be used to derive the output clock rate: * - 25 MHz Crystal * - System clock * - PLL channel 0 (slow clock) * - PLL channel 1 (fast clock) */ static int __get_mdiv(struct iproc_arm_pll *pll) { … } static unsigned int __get_ndiv(struct iproc_arm_pll *pll) { … } /* * The output frequency of the ARM PLL is calculated based on the ARM PLL * divider values: * pdiv = ARM PLL pre-divider * ndiv = ARM PLL multiplier * mdiv = ARM PLL post divider * * The frequency is calculated by: * ((ndiv * parent clock rate) / pdiv) / mdiv */ static unsigned long iproc_arm_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops iproc_arm_pll_ops = …; void __init iproc_armpll_setup(struct device_node *node) { … }
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