// SPDX-License-Identifier: GPL-2.0-or-later /* * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards * * Author Andreas Eversberg ([email protected]) * ported to mqueue mechanism: * Peter Sprenger (sprengermoving-bytes.de) * * inspired by existing hfc-pci driver: * Copyright 1999 by Werner Cornelius ([email protected]) * Copyright 2008 by Karsten Keil ([email protected]) * Copyright 2008 by Andreas Eversberg ([email protected]) * * Thanks to Cologne Chip AG for this great controller! */ /* * module parameters: * type: * By default (0), the card is automatically detected. * Or use the following combinations: * Bit 0-7 = 0x00001 = HFC-E1 (1 port) * or Bit 0-7 = 0x00004 = HFC-4S (4 ports) * or Bit 0-7 = 0x00008 = HFC-8S (8 ports) * Bit 8 = 0x00100 = uLaw (instead of aLaw) * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware * Bit 10 = spare * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto) * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto) * Bit 13 = spare * Bit 14 = 0x04000 = Use external ram (128K) * Bit 15 = 0x08000 = Use external ram (512K) * Bit 16 = 0x10000 = Use 64 timeslots instead of 32 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else * Bit 18 = spare * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog) * (all other bits are reserved and shall be 0) * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM * bus (PCM master) * * port: (optional or required for all ports on all installed cards) * HFC-4S/HFC-8S only bits: * Bit 0 = 0x001 = Use master clock for this S/T interface * (ony once per chip). * Bit 1 = 0x002 = transmitter line setup (non capacitive mode) * Don't use this unless you know what you are doing! * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing) * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock * received from port 1 * * HFC-E1 only bits: * Bit 0 = 0x0001 = interface: 0=copper, 1=optical * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode) * Bit 2 = 0x0004 = Report LOS * Bit 3 = 0x0008 = Report AIS * Bit 4 = 0x0010 = Report SLIP * Bit 5 = 0x0020 = Report RDI * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame * mode instead. * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode. * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode. * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL. * (E1 only) * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0 * for default. * (all other bits are reserved and shall be 0) * * debug: * NOTE: only one debug value must be given for all cards * enable debugging (see hfc_multi.h for debug options) * * poll: * NOTE: only one poll value must be given for all cards * Give the number of samples for each fifo process. * By default 128 is used. Decrease to reduce delay, increase to * reduce cpu load. If unsure, don't mess with it! * Valid is 8, 16, 32, 64, 128, 256. * * pcm: * NOTE: only one pcm value must be given for every card. * The PCM bus id tells the mISDNdsp module about the connected PCM bus. * By default (0), the PCM bus id is 100 for the card that is PCM master. * If multiple cards are PCM master (because they are not interconnected), * each card with PCM master will have increasing PCM id. * All PCM busses with the same ID are expected to be connected and have * common time slots slots. * Only one chip of the PCM bus must be master, the others slave. * -1 means no support of PCM bus not even. * Omit this value, if all cards are interconnected or none is connected. * If unsure, don't give this parameter. * * dmask and bmask: * NOTE: One dmask value must be given for every HFC-E1 card. * If omitted, the E1 card has D-channel on time slot 16, which is default. * dmask is a 32 bit mask. The bit must be set for an alternate time slot. * If multiple bits are set, multiple virtual card fragments are created. * For each bit set, a bmask value must be given. Each bit on the bmask * value stands for a B-channel. The bmask may not overlap with dmask or * with other bmask values for that card. * Example: dmask=0x00020002 bmask=0x0000fffc,0xfffc0000 * This will create one fragment with D-channel on slot 1 with * B-channels on slots 2..15, and a second fragment with D-channel * on slot 17 with B-channels on slot 18..31. Slot 16 is unused. * If bit 0 is set (dmask=0x00000001) the D-channel is on slot 0 and will * not function. * Example: dmask=0x00000001 bmask=0xfffffffe * This will create a port with all 31 usable timeslots as * B-channels. * If no bits are set on bmask, no B-channel is created for that fragment. * Example: dmask=0xfffffffe bmask=0,0,0,0.... (31 0-values for bmask) * This will create 31 ports with one D-channel only. * If you don't know how to use it, you don't need it! * * iomode: * NOTE: only one mode value must be given for every card. * -> See hfc_multi.h for HFC_IO_MODE_* values * By default, the IO mode is pci memory IO (MEMIO). * Some cards require specific IO mode, so it cannot be changed. * It may be useful to set IO mode to register io (REGIO) to solve * PCI bridge problems. * If unsure, don't give this parameter. * * clockdelay_nt: * NOTE: only one clockdelay_nt value must be given once for all cards. * Give the value of the clock control register (A_ST_CLK_DLY) * of the S/T interfaces in NT mode. * This register is needed for the TBR3 certification, so don't change it. * * clockdelay_te: * NOTE: only one clockdelay_te value must be given once * Give the value of the clock control register (A_ST_CLK_DLY) * of the S/T interfaces in TE mode. * This register is needed for the TBR3 certification, so don't change it. * * clock: * NOTE: only one clock value must be given once * Selects interface with clock source for mISDN and applications. * Set to card number starting with 1. Set to -1 to disable. * By default, the first card is used as clock source. * * hwid: * NOTE: only one hwid value must be given once * Enable special embedded devices with XHFC controllers. */ /* * debug register access (never use this, it will flood your system log) * #define HFC_REGISTER_DEBUG */ #define HFC_MULTI_VERSION … #include <linux/interrupt.h> #include <linux/module.h> #include <linux/slab.h> #include <linux/pci.h> #include <linux/delay.h> #include <linux/mISDNhw.h> #include <linux/mISDNdsp.h> /* #define IRQCOUNT_DEBUG #define IRQ_DEBUG */ #include "hfc_multi.h" #ifdef ECHOPREP #include "gaintab.h" #endif #define MAX_CARDS … #define MAX_PORTS … #define MAX_FRAGS … static LIST_HEAD(HFClist); static DEFINE_SPINLOCK(HFClock); /* global hfc list lock */ static void ph_state_change(struct dchannel *); static struct hfc_multi *syncmaster; static int plxsd_master; /* if we have a master card (yet) */ static DEFINE_SPINLOCK(plx_lock); /* may not acquire other lock inside */ #define TYP_E1 … #define TYP_4S … #define TYP_8S … static int poll_timer = …; /* default = 128 samples = 16ms */ /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */ static int nt_t1_count[] = …; #define CLKDEL_TE … #define CLKDEL_NT … #define DIP_4S … #define DIP_8S … #define DIP_E1 … /* * module stuff */ static uint type[MAX_CARDS]; static int pcm[MAX_CARDS]; static uint dmask[MAX_CARDS]; static uint bmask[MAX_FRAGS]; static uint iomode[MAX_CARDS]; static uint port[MAX_PORTS]; static uint debug; static uint poll; static int clock; static uint timer; static uint clockdelay_te = …; static uint clockdelay_nt = …; #define HWID_NONE … #define HWID_MINIP4 … #define HWID_MINIP8 … #define HWID_MINIP16 … static uint hwid = …; static int HFC_cnt, E1_cnt, bmask_cnt, Port_cnt, PCM_cnt = …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_VERSION(…); module_param(debug, uint, S_IRUGO | S_IWUSR); module_param(poll, uint, S_IRUGO | S_IWUSR); module_param(clock, int, S_IRUGO | S_IWUSR); module_param(timer, uint, S_IRUGO | S_IWUSR); module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR); module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR); module_param_array(…); module_param_array(…); module_param_array(…); module_param_array(…); module_param_array(…); module_param_array(…); module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */ #ifdef HFC_REGISTER_DEBUG #define HFC_outb … #define HFC_outb_nodebug … #define HFC_inb … #define HFC_inb_nodebug … #define HFC_inw … #define HFC_inw_nodebug … #define HFC_wait … #define HFC_wait_nodebug … #else #define HFC_outb(hc, reg, val) … #define HFC_outb_nodebug(hc, reg, val) … #define HFC_inb(hc, reg) … #define HFC_inb_nodebug(hc, reg) … #define HFC_inw(hc, reg) … #define HFC_inw_nodebug(hc, reg) … #define HFC_wait(hc) … #define HFC_wait_nodebug(hc) … #endif #ifdef CONFIG_MISDN_HFCMULTI_8xx #include "hfc_multi_8xx.h" #endif /* HFC_IO_MODE_PCIMEM */ static void #ifdef HFC_REGISTER_DEBUG HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val, const char *function, int line) #else HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val) #endif { … } static u_char #ifdef HFC_REGISTER_DEBUG HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) #else HFC_inb_pcimem(struct hfc_multi *hc, u_char reg) #endif { … } static u_short #ifdef HFC_REGISTER_DEBUG HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) #else HFC_inw_pcimem(struct hfc_multi *hc, u_char reg) #endif { … } static void #ifdef HFC_REGISTER_DEBUG HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line) #else HFC_wait_pcimem(struct hfc_multi *hc) #endif { … } /* HFC_IO_MODE_REGIO */ static void #ifdef HFC_REGISTER_DEBUG HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val, const char *function, int line) #else HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val) #endif { … } static u_char #ifdef HFC_REGISTER_DEBUG HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) #else HFC_inb_regio(struct hfc_multi *hc, u_char reg) #endif { … } static u_short #ifdef HFC_REGISTER_DEBUG HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) #else HFC_inw_regio(struct hfc_multi *hc, u_char reg) #endif { … } static void #ifdef HFC_REGISTER_DEBUG HFC_wait_regio(struct hfc_multi *hc, const char *function, int line) #else HFC_wait_regio(struct hfc_multi *hc) #endif { … } #ifdef HFC_REGISTER_DEBUG static void HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val, const char *function, int line) { char regname[256] = "", bits[9] = "xxxxxxxx"; int i; i = -1; while (hfc_register_names[++i].name) { if (hfc_register_names[i].reg == reg) strcat(regname, hfc_register_names[i].name); } if (regname[0] == '\0') strcpy(regname, "register"); bits[7] = '0' + (!!(val & 1)); bits[6] = '0' + (!!(val & 2)); bits[5] = '0' + (!!(val & 4)); bits[4] = '0' + (!!(val & 8)); bits[3] = '0' + (!!(val & 16)); bits[2] = '0' + (!!(val & 32)); bits[1] = '0' + (!!(val & 64)); bits[0] = '0' + (!!(val & 128)); printk(KERN_DEBUG "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n", hc->id, reg, regname, val, bits, function, line); HFC_outb_nodebug(hc, reg, val); } static u_char HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) { char regname[256] = "", bits[9] = "xxxxxxxx"; u_char val = HFC_inb_nodebug(hc, reg); int i; i = 0; while (hfc_register_names[i++].name) ; while (hfc_register_names[++i].name) { if (hfc_register_names[i].reg == reg) strcat(regname, hfc_register_names[i].name); } if (regname[0] == '\0') strcpy(regname, "register"); bits[7] = '0' + (!!(val & 1)); bits[6] = '0' + (!!(val & 2)); bits[5] = '0' + (!!(val & 4)); bits[4] = '0' + (!!(val & 8)); bits[3] = '0' + (!!(val & 16)); bits[2] = '0' + (!!(val & 32)); bits[1] = '0' + (!!(val & 64)); bits[0] = '0' + (!!(val & 128)); printk(KERN_DEBUG "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n", hc->id, reg, regname, val, bits, function, line); return val; } static u_short HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) { char regname[256] = ""; u_short val = HFC_inw_nodebug(hc, reg); int i; i = 0; while (hfc_register_names[i++].name) ; while (hfc_register_names[++i].name) { if (hfc_register_names[i].reg == reg) strcat(regname, hfc_register_names[i].name); } if (regname[0] == '\0') strcpy(regname, "register"); printk(KERN_DEBUG "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n", hc->id, reg, regname, val, function, line); return val; } static void HFC_wait_debug(struct hfc_multi *hc, const char *function, int line) { printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n", hc->id, function, line); HFC_wait_nodebug(hc); } #endif /* write fifo data (REGIO) */ static void write_fifo_regio(struct hfc_multi *hc, u_char *data, int len) { … } /* write fifo data (PCIMEM) */ static void write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) { … } /* read fifo data (REGIO) */ static void read_fifo_regio(struct hfc_multi *hc, u_char *data, int len) { … } /* read fifo data (PCIMEM) */ static void read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) { … } static void enable_hwirq(struct hfc_multi *hc) { … } static void disable_hwirq(struct hfc_multi *hc) { … } #define NUM_EC … #define MAX_TDM_CHAN … static inline void enablepcibridge(struct hfc_multi *c) { … } static inline void disablepcibridge(struct hfc_multi *c) { … } static inline unsigned char readpcibridge(struct hfc_multi *hc, unsigned char address) { … } static inline void writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data) { … } static inline void cpld_set_reg(struct hfc_multi *hc, unsigned char reg) { … } static inline void cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val) { … } static inline void vpm_write_address(struct hfc_multi *hc, unsigned short addr) { … } static inline unsigned char vpm_in(struct hfc_multi *c, int which, unsigned short addr) { … } static inline void vpm_out(struct hfc_multi *c, int which, unsigned short addr, unsigned char data) { … } static void vpm_init(struct hfc_multi *wc) { … } #ifdef UNUSED static void vpm_check(struct hfc_multi *hctmp) { unsigned char gpi2; gpi2 = HFC_inb(hctmp, R_GPI_IN2); if ((gpi2 & 0x3) != 0x3) printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2); } #endif /* UNUSED */ /* * Interface to enable/disable the HW Echocan * * these functions are called within a spin_lock_irqsave on * the channel instance lock, so we are not disturbed by irqs * * we can later easily change the interface to make other * things configurable, for now we configure the taps * */ static void vpm_echocan_on(struct hfc_multi *hc, int ch, int taps) { … } static void vpm_echocan_off(struct hfc_multi *hc, int ch) { … } /* * Speech Design resync feature * NOTE: This is called sometimes outside interrupt handler. * We must lock irqsave, so no other interrupt (other card) will occur! * Also multiple interrupts may nest, so must lock each access (lists, card)! */ static inline void hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm) { … } /* This must be called AND hc must be locked irqsave!!! */ static inline void plxsd_checksync(struct hfc_multi *hc, int rm) { … } /* * free hardware resources used by driver */ static void release_io_hfcmulti(struct hfc_multi *hc) { … } /* * function called to reset the HFC chip. A complete software reset of chip * and fifos is done. All configuration of the chip is done. */ static int init_chip(struct hfc_multi *hc) { … } /* * control the watchdog */ static void hfcmulti_watchdog(struct hfc_multi *hc) { … } /* * output leds */ static void hfcmulti_leds(struct hfc_multi *hc) { … } /* * read dtmf coefficients */ static void hfcmulti_dtmf(struct hfc_multi *hc) { … } /* * fill fifo as much as possible */ static void hfcmulti_tx(struct hfc_multi *hc, int ch) { … } /* NOTE: only called if E1 card is in active state */ static void hfcmulti_rx(struct hfc_multi *hc, int ch) { … } /* * Interrupt handler */ static void signal_state_up(struct dchannel *dch, int info, char *msg) { … } static inline void handle_timer_irq(struct hfc_multi *hc) { … } static void ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech) { … } static void fifo_irq(struct hfc_multi *hc, int block) { … } #ifdef IRQ_DEBUG int irqsem; #endif static irqreturn_t hfcmulti_interrupt(int intno, void *dev_id) { … } /* * timer callback for D-chan busy resolution. Currently no function */ static void hfcmulti_dbusy_timer(struct timer_list *t) { … } /* * activate/deactivate hardware for selected channels and mode * * configure B-channel with the given protocol * ch eqals to the HFC-channel (0-31) * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31 * for S/T, 1-31 for E1) * the hdlc interrupts will be set/unset */ static int mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx, int bank_tx, int slot_rx, int bank_rx) { … } /* * connect/disconnect PCM */ static void hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx, int slot_rx, int bank_rx) { … } /* * set/disable conference */ static void hfcmulti_conf(struct hfc_multi *hc, int ch, int num) { … } /* * set/disable sample loop */ /* NOTE: this function is experimental and therefore disabled */ /* * Layer 1 callback function */ static int hfcm_l1callback(struct dchannel *dch, u_int cmd) { … } /* * Layer2 -> Layer 1 Transfer */ static int handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb) { … } static void deactivate_bchannel(struct bchannel *bch) { … } static int handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb) { … } /* * bchannel control function */ static int channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq) { … } static int hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg) { … } /* * handle D-channel events * * handle state change event */ static void ph_state_change(struct dchannel *dch) { … } /* * called for card mode init message */ static void hfcmulti_initmode(struct dchannel *dch) { … } static int open_dchannel(struct hfc_multi *hc, struct dchannel *dch, struct channel_req *rq) { … } static int open_bchannel(struct hfc_multi *hc, struct dchannel *dch, struct channel_req *rq) { … } /* * device control function */ static int channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq) { … } static int hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg) { … } static int clockctl(void *priv, int enable) { … } /* * initialize the card */ /* * start timer irq, wait some time and check if we have interrupts. * if not, reset chip and try again. */ static int init_card(struct hfc_multi *hc) { … } /* * find pci device and set it up */ static int setup_pci(struct hfc_multi *hc, struct pci_dev *pdev, const struct pci_device_id *ent) { … } /* * remove port */ static void release_port(struct hfc_multi *hc, struct dchannel *dch) { … } static void release_card(struct hfc_multi *hc) { … } static void init_e1_port_hw(struct hfc_multi *hc, struct hm_map *m) { … } static int init_e1_port(struct hfc_multi *hc, struct hm_map *m, int pt) { … } static int init_multi_port(struct hfc_multi *hc, int pt) { … } static int hfcmulti_init(struct hm_map *m, struct pci_dev *pdev, const struct pci_device_id *ent) { … } static void hfc_remove_pci(struct pci_dev *pdev) { … } #define VENDOR_CCD … #define VENDOR_BN … #define VENDOR_DIG … #define VENDOR_JH … #define VENDOR_PRIM … static const struct hm_map hfcm_map[] = …; #undef H #define H … static const struct pci_device_id hfmultipci_ids[] = …; #undef H MODULE_DEVICE_TABLE(pci, hfmultipci_ids); static int hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { … } static struct pci_driver hfcmultipci_driver = …; static void __exit HFCmulti_cleanup(void) { … } static int __init HFCmulti_init(void) { … } module_init(…) …; module_exit(HFCmulti_cleanup);
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