/* SPDX-License-Identifier: GPL-2.0 */ /* * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver. * Originally split out from the skx_edac driver. * * Copyright (c) 2018, Intel Corporation. */ #ifndef _SKX_COMM_EDAC_H #define _SKX_COMM_EDAC_H #include <linux/bits.h> #include <asm/mce.h> #define MSG_SIZE … /* * Debug macros */ #define skx_printk(level, fmt, arg...) … #define skx_mc_printk(mci, level, fmt, arg...) … /* * Get a bit field at register value <v>, from bit <lo> to bit <hi> */ #define GET_BITFIELD(v, lo, hi) … #define SKX_NUM_IMC … #define SKX_NUM_CHANNELS … #define SKX_NUM_DIMMS … #define I10NM_NUM_DDR_IMC … #define I10NM_NUM_DDR_CHANNELS … #define I10NM_NUM_DDR_DIMMS … #define I10NM_NUM_HBM_IMC … #define I10NM_NUM_HBM_CHANNELS … #define I10NM_NUM_HBM_DIMMS … #define I10NM_NUM_IMC … #define I10NM_NUM_CHANNELS … #define I10NM_NUM_DIMMS … #define NUM_IMC … #define NUM_CHANNELS … #define NUM_DIMMS … #define IS_DIMM_PRESENT(r) … #define IS_NVDIMM_PRESENT(r, i) … #define MCI_MISC_ECC_MODE(m) … #define MCI_MISC_ECC_DDRT … /* * According to Intel Architecture spec vol 3B, * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding" * memory errors should fit one of these masks: * 000f 0000 1mmm cccc (binary) * 000f 0010 1mmm cccc (binary) [RAM used as cache] * where: * f = Correction Report Filtering Bit. If 1, subsequent errors * won't be shown * mmm = error type * cccc = channel */ #define MCACOD_MEM_ERR_MASK … /* * Errors from either the memory of the 1-level memory system or the * 2nd level memory (the slow "far" memory) of the 2-level memory system. */ #define MCACOD_MEM_CTL_ERR … /* * Errors from the 1st level memory (the fast "near" memory as cache) * of the 2-level memory system. */ #define MCACOD_EXT_MEM_ERR … /* * Each cpu socket contains some pci devices that provide global * information, and also some that are local to each of the two * memory controllers on the die. */ struct skx_dev { … }; struct skx_pvt { … }; enum type { … }; enum { … }; #define BIT_NM_MEMCTRL … #define BIT_NM_CHANNEL … #define BIT_NM_DIMM … #define BIT_NM_CS … struct decoded_addr { … }; struct pci_bdf { … }; struct res_config { … }; get_dimm_config_f; skx_decode_f; skx_show_retry_log_f; int skx_adxl_get(void); void skx_adxl_put(void); void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log); void skx_set_mem_cfg(bool mem_cfg_2lm); int skx_get_src_id(struct skx_dev *d, int off, u8 *id); int skx_get_node_id(struct skx_dev *d, u8 *id); int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list); int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm); int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, struct skx_imc *imc, int chan, int dimmno, struct res_config *cfg); int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc, int chan, int dimmno, const char *mod_str); int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev, const char *ctl_name, const char *mod_str, get_dimm_config_f get_dimm_config, struct res_config *cfg); int skx_mce_check_error(struct notifier_block *nb, unsigned long val, void *data); void skx_remove(void); #endif /* _SKX_COMM_EDAC_H */
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