// SPDX-License-Identifier: GPL-2.0 /* * Driver for Intel(R) 10nm server memory controller. * Copyright (c) 2019, Intel Corporation. * */ #include <linux/kernel.h> #include <linux/io.h> #include <asm/cpu_device_id.h> #include <asm/intel-family.h> #include <asm/mce.h> #include "edac_module.h" #include "skx_common.h" #define I10NM_REVISION … #define EDAC_MOD_STR … /* Debug macros */ #define i10nm_printk(level, fmt, arg...) … #define I10NM_GET_SCK_BAR(d, reg) … #define I10NM_GET_IMC_BAR(d, i, reg) … #define I10NM_GET_SAD(d, offset, i, reg) … #define I10NM_GET_HBM_IMC_BAR(d, reg) … #define I10NM_GET_CAPID3_CFG(d, reg) … #define I10NM_GET_CAPID5_CFG(d, reg) … #define I10NM_GET_DIMMMTR(m, i, j) … #define I10NM_GET_MCDDRTCFG(m, i) … #define I10NM_GET_MCMTR(m, i) … #define I10NM_GET_AMAP(m, i) … #define I10NM_GET_REG32(m, i, offset) … #define I10NM_GET_REG64(m, i, offset) … #define I10NM_SET_REG32(m, i, offset, v) … #define I10NM_GET_SCK_MMIO_BASE(reg) … #define I10NM_GET_IMC_MMIO_OFFSET(reg) … #define I10NM_GET_IMC_MMIO_SIZE(reg) … #define I10NM_GET_HBM_IMC_MMIO_OFFSET(reg) … #define I10NM_GNR_IMC_MMIO_OFFSET … #define I10NM_GNR_IMC_MMIO_SIZE … #define I10NM_HBM_IMC_MMIO_SIZE … #define I10NM_DDR_IMC_CH_CNT(reg) … #define I10NM_IS_HBM_PRESENT(reg) … #define I10NM_IS_HBM_IMC(reg) … #define I10NM_MAX_SAD … #define I10NM_SAD_ENABLE(reg) … #define I10NM_SAD_NM_CACHEABLE(reg) … #define RETRY_RD_ERR_LOG_UC … #define RETRY_RD_ERR_LOG_NOOVER … #define RETRY_RD_ERR_LOG_EN … #define RETRY_RD_ERR_LOG_NOOVER_UC … #define RETRY_RD_ERR_LOG_OVER_UC_V … static struct list_head *i10nm_edac_list; static struct res_config *res_cfg; static int retry_rd_err_log; static int decoding_via_mca; static bool mem_cfg_2lm; static u32 offsets_scrub_icx[] = …; static u32 offsets_scrub_spr[] = …; static u32 offsets_scrub_spr_hbm0[] = …; static u32 offsets_scrub_spr_hbm1[] = …; static u32 offsets_demand_icx[] = …; static u32 offsets_demand_spr[] = …; static u32 offsets_demand2_spr[] = …; static u32 offsets_demand_spr_hbm0[] = …; static u32 offsets_demand_spr_hbm1[] = …; static void __enable_retry_rd_err_log(struct skx_imc *imc, int chan, bool enable, u32 *offsets_scrub, u32 *offsets_demand, u32 *offsets_demand2) { … } static void enable_retry_rd_err_log(bool enable) { … } static void show_retry_rd_err_log(struct decoded_addr *res, char *msg, int len, bool scrub_err) { … } static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus, unsigned int dev, unsigned int fun) { … } /** * i10nm_get_imc_num() - Get the number of present DDR memory controllers. * * @cfg : The pointer to the structure of EDAC resource configurations. * * For Granite Rapids CPUs, the number of present DDR memory controllers read * at runtime overwrites the value statically configured in @cfg->ddr_imc_num. * For other CPUs, the number of present DDR memory controllers is statically * configured in @cfg->ddr_imc_num. * * RETURNS : 0 on success, < 0 on failure. */ static int i10nm_get_imc_num(struct res_config *cfg) { … } static bool i10nm_check_2lm(struct res_config *cfg) { … } /* * Check whether the error comes from DDRT by ICX/Tremont/SPR model specific error code. * Refer to SDM vol3B 17.11.3/17.13.2 Intel IMC MC error codes for IA32_MCi_STATUS. */ static bool i10nm_mscod_is_ddrt(u32 mscod) { … } static bool i10nm_mc_decode_available(struct mce *mce) { … } static bool i10nm_mc_decode(struct decoded_addr *res) { … } /** * get_gnr_mdev() - Get the PCI device of the @logical_idx-th DDR memory controller. * * @d : The pointer to the structure of CPU socket EDAC device. * @logical_idx : The logical index of the present memory controller (0 ~ max present MC# - 1). * @physical_idx : To store the corresponding physical index of @logical_idx. * * RETURNS : The PCI device of the @logical_idx-th DDR memory controller, NULL on failure. */ static struct pci_dev *get_gnr_mdev(struct skx_dev *d, int logical_idx, int *physical_idx) { … } /** * get_ddr_munit() - Get the resource of the i-th DDR memory controller. * * @d : The pointer to the structure of CPU socket EDAC device. * @i : The index of the CPU socket relative DDR memory controller. * @offset : To store the MMIO offset of the i-th DDR memory controller. * @size : To store the MMIO size of the i-th DDR memory controller. * * RETURNS : The PCI device of the i-th DDR memory controller, NULL on failure. */ static struct pci_dev *get_ddr_munit(struct skx_dev *d, int i, u32 *offset, unsigned long *size) { … } /** * i10nm_imc_absent() - Check whether the memory controller @imc is absent * * @imc : The pointer to the structure of memory controller EDAC device. * * RETURNS : true if the memory controller EDAC device is absent, false otherwise. */ static bool i10nm_imc_absent(struct skx_imc *imc) { … } static int i10nm_get_ddr_munits(void) { … } static bool i10nm_check_hbm_imc(struct skx_dev *d) { … } static int i10nm_get_hbm_munits(void) { … } static struct res_config i10nm_cfg0 = …; static struct res_config i10nm_cfg1 = …; static struct res_config spr_cfg = …; static struct res_config gnr_cfg = …; static const struct x86_cpu_id i10nm_cpuids[] = …; MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids); static bool i10nm_check_ecc(struct skx_imc *imc, int chan) { … } static int i10nm_get_dimm_config(struct mem_ctl_info *mci, struct res_config *cfg) { … } static struct notifier_block i10nm_mce_dec = …; #ifdef CONFIG_EDAC_DEBUG /* * Debug feature. * Exercise the address decode logic by writing an address to * /sys/kernel/debug/edac/i10nm_test/addr. */ static struct dentry *i10nm_test; static int debugfs_u64_set(void *data, u64 val) { … } DEFINE_SIMPLE_ATTRIBUTE(…); static void setup_i10nm_debug(void) { … } static void teardown_i10nm_debug(void) { … } #else static inline void setup_i10nm_debug(void) {} static inline void teardown_i10nm_debug(void) {} #endif /*CONFIG_EDAC_DEBUG*/ static int __init i10nm_init(void) { … } static void __exit i10nm_exit(void) { … } module_init(…) …; module_exit(i10nm_exit); static int set_decoding_via_mca(const char *buf, const struct kernel_param *kp) { … } static const struct kernel_param_ops decoding_via_mca_param_ops = …; module_param_cb(…); MODULE_PARM_DESC(…) …; module_param(retry_rd_err_log, int, 0444); MODULE_PARM_DESC(…) …; MODULE_LICENSE(…) …; MODULE_DESCRIPTION(…) …;
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