// SPDX-License-Identifier: GPL-2.0-or-later /* * APM X-Gene SoC EDAC (error detection and correction) * * Copyright (c) 2015, Applied Micro Circuits Corporation * Author: Feng Kan <[email protected]> * Loc Ho <[email protected]> */ #include <linux/ctype.h> #include <linux/edac.h> #include <linux/interrupt.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/regmap.h> #include "edac_module.h" #define EDAC_MOD_STR … /* Global error configuration status registers (CSR) */ #define PCPHPERRINTSTS … #define PCPHPERRINTMSK … #define MCU_CTL_ERR_MASK … #define IOB_PA_ERR_MASK … #define IOB_BA_ERR_MASK … #define IOB_XGIC_ERR_MASK … #define IOB_RB_ERR_MASK … #define L3C_UNCORR_ERR_MASK … #define MCU_UNCORR_ERR_MASK … #define PMD3_MERR_MASK … #define PMD2_MERR_MASK … #define PMD1_MERR_MASK … #define PMD0_MERR_MASK … #define PCPLPERRINTSTS … #define PCPLPERRINTMSK … #define CSW_SWITCH_TRACE_ERR_MASK … #define L3C_CORR_ERR_MASK … #define MCU_CORR_ERR_MASK … #define MEMERRINTSTS … #define MEMERRINTMSK … struct xgene_edac { … }; static void xgene_edac_pcp_rd(struct xgene_edac *edac, u32 reg, u32 *val) { … } static void xgene_edac_pcp_clrbits(struct xgene_edac *edac, u32 reg, u32 bits_mask) { … } static void xgene_edac_pcp_setbits(struct xgene_edac *edac, u32 reg, u32 bits_mask) { … } /* Memory controller error CSR */ #define MCU_MAX_RANK … #define MCU_RANK_STRIDE … #define MCUGECR … #define MCU_GECR_DEMANDUCINTREN_MASK … #define MCU_GECR_BACKUCINTREN_MASK … #define MCU_GECR_CINTREN_MASK … #define MUC_GECR_MCUADDRERREN_MASK … #define MCUGESR … #define MCU_GESR_ADDRNOMATCH_ERR_MASK … #define MCU_GESR_ADDRMULTIMATCH_ERR_MASK … #define MCU_GESR_PHYP_ERR_MASK … #define MCUESRR0 … #define MCU_ESRR_MULTUCERR_MASK … #define MCU_ESRR_BACKUCERR_MASK … #define MCU_ESRR_DEMANDUCERR_MASK … #define MCU_ESRR_CERR_MASK … #define MCUESRRA0 … #define MCUEBLRR0 … #define MCU_EBLRR_ERRBANK_RD(src) … #define MCUERCRR0 … #define MCU_ERCRR_ERRROW_RD(src) … #define MCU_ERCRR_ERRCOL_RD(src) … #define MCUSBECNT0 … #define MCU_SBECNT_COUNT(src) … #define CSW_CSWCR … #define CSW_CSWCR_DUALMCB_MASK … #define MCBADDRMR … #define MCBADDRMR_MCU_INTLV_MODE_MASK … #define MCBADDRMR_DUALMCU_MODE_MASK … #define MCBADDRMR_MCB_INTLV_MODE_MASK … #define MCBADDRMR_ADDRESS_MODE_MASK … struct xgene_edac_mc_ctx { … }; static ssize_t xgene_edac_mc_err_inject_write(struct file *file, const char __user *data, size_t count, loff_t *ppos) { … } static const struct file_operations xgene_edac_mc_debug_inject_fops = …; static void xgene_edac_mc_create_debugfs_node(struct mem_ctl_info *mci) { … } static void xgene_edac_mc_check(struct mem_ctl_info *mci) { … } static void xgene_edac_mc_irq_ctl(struct mem_ctl_info *mci, bool enable) { … } static int xgene_edac_mc_is_active(struct xgene_edac_mc_ctx *ctx, int mc_idx) { … } static int xgene_edac_mc_add(struct xgene_edac *edac, struct device_node *np) { … } static int xgene_edac_mc_remove(struct xgene_edac_mc_ctx *mcu) { … } /* CPU L1/L2 error CSR */ #define MAX_CPU_PER_PMD … #define CPU_CSR_STRIDE … #define CPU_L2C_PAGE … #define CPU_MEMERR_L2C_PAGE … #define CPU_MEMERR_CPU_PAGE … #define MEMERR_CPU_ICFECR_PAGE_OFFSET … #define MEMERR_CPU_ICFESR_PAGE_OFFSET … #define MEMERR_CPU_ICFESR_ERRWAY_RD(src) … #define MEMERR_CPU_ICFESR_ERRINDEX_RD(src) … #define MEMERR_CPU_ICFESR_ERRINFO_RD(src) … #define MEMERR_CPU_ICFESR_ERRTYPE_RD(src) … #define MEMERR_CPU_ICFESR_MULTCERR_MASK … #define MEMERR_CPU_ICFESR_CERR_MASK … #define MEMERR_CPU_LSUESR_PAGE_OFFSET … #define MEMERR_CPU_LSUESR_ERRWAY_RD(src) … #define MEMERR_CPU_LSUESR_ERRINDEX_RD(src) … #define MEMERR_CPU_LSUESR_ERRINFO_RD(src) … #define MEMERR_CPU_LSUESR_ERRTYPE_RD(src) … #define MEMERR_CPU_LSUESR_MULTCERR_MASK … #define MEMERR_CPU_LSUESR_CERR_MASK … #define MEMERR_CPU_LSUECR_PAGE_OFFSET … #define MEMERR_CPU_MMUECR_PAGE_OFFSET … #define MEMERR_CPU_MMUESR_PAGE_OFFSET … #define MEMERR_CPU_MMUESR_ERRWAY_RD(src) … #define MEMERR_CPU_MMUESR_ERRINDEX_RD(src) … #define MEMERR_CPU_MMUESR_ERRINFO_RD(src) … #define MEMERR_CPU_MMUESR_ERRREQSTR_LSU_MASK … #define MEMERR_CPU_MMUESR_ERRTYPE_RD(src) … #define MEMERR_CPU_MMUESR_MULTCERR_MASK … #define MEMERR_CPU_MMUESR_CERR_MASK … #define MEMERR_CPU_ICFESRA_PAGE_OFFSET … #define MEMERR_CPU_LSUESRA_PAGE_OFFSET … #define MEMERR_CPU_MMUESRA_PAGE_OFFSET … #define MEMERR_L2C_L2ECR_PAGE_OFFSET … #define MEMERR_L2C_L2ESR_PAGE_OFFSET … #define MEMERR_L2C_L2ESR_ERRSYN_RD(src) … #define MEMERR_L2C_L2ESR_ERRWAY_RD(src) … #define MEMERR_L2C_L2ESR_ERRCPU_RD(src) … #define MEMERR_L2C_L2ESR_ERRGROUP_RD(src) … #define MEMERR_L2C_L2ESR_ERRACTION_RD(src) … #define MEMERR_L2C_L2ESR_ERRTYPE_RD(src) … #define MEMERR_L2C_L2ESR_MULTUCERR_MASK … #define MEMERR_L2C_L2ESR_MULTICERR_MASK … #define MEMERR_L2C_L2ESR_UCERR_MASK … #define MEMERR_L2C_L2ESR_ERR_MASK … #define MEMERR_L2C_L2EALR_PAGE_OFFSET … #define CPUX_L2C_L2RTOCR_PAGE_OFFSET … #define MEMERR_L2C_L2EAHR_PAGE_OFFSET … #define CPUX_L2C_L2RTOSR_PAGE_OFFSET … #define MEMERR_L2C_L2RTOSR_MULTERR_MASK … #define MEMERR_L2C_L2RTOSR_ERR_MASK … #define CPUX_L2C_L2RTOALR_PAGE_OFFSET … #define CPUX_L2C_L2RTOAHR_PAGE_OFFSET … #define MEMERR_L2C_L2ESRA_PAGE_OFFSET … /* * Processor Module Domain (PMD) context - Context for a pair of processors. * Each PMD consists of 2 CPUs and a shared L2 cache. Each CPU consists of * its own L1 cache. */ struct xgene_edac_pmd_ctx { … }; static void xgene_edac_pmd_l1_check(struct edac_device_ctl_info *edac_dev, int cpu_idx) { … } static void xgene_edac_pmd_l2_check(struct edac_device_ctl_info *edac_dev) { … } static void xgene_edac_pmd_check(struct edac_device_ctl_info *edac_dev) { … } static void xgene_edac_pmd_cpu_hw_cfg(struct edac_device_ctl_info *edac_dev, int cpu) { … } static void xgene_edac_pmd_hw_cfg(struct edac_device_ctl_info *edac_dev) { … } static void xgene_edac_pmd_hw_ctl(struct edac_device_ctl_info *edac_dev, bool enable) { … } static ssize_t xgene_edac_pmd_l1_inject_ctrl_write(struct file *file, const char __user *data, size_t count, loff_t *ppos) { … } static ssize_t xgene_edac_pmd_l2_inject_ctrl_write(struct file *file, const char __user *data, size_t count, loff_t *ppos) { … } static const struct file_operations xgene_edac_pmd_debug_inject_fops[] = …; static void xgene_edac_pmd_create_debugfs_nodes(struct edac_device_ctl_info *edac_dev) { … } static int xgene_edac_pmd_available(u32 efuse, int pmd) { … } static int xgene_edac_pmd_add(struct xgene_edac *edac, struct device_node *np, int version) { … } static int xgene_edac_pmd_remove(struct xgene_edac_pmd_ctx *pmd) { … } /* L3 Error device */ #define L3C_ESR … #define L3C_ESR_DATATAG_MASK … #define L3C_ESR_MULTIHIT_MASK … #define L3C_ESR_UCEVICT_MASK … #define L3C_ESR_MULTIUCERR_MASK … #define L3C_ESR_MULTICERR_MASK … #define L3C_ESR_UCERR_MASK … #define L3C_ESR_CERR_MASK … #define L3C_ESR_UCERRINTR_MASK … #define L3C_ESR_CERRINTR_MASK … #define L3C_ECR … #define L3C_ECR_UCINTREN … #define L3C_ECR_CINTREN … #define L3C_UCERREN … #define L3C_CERREN … #define L3C_ELR … #define L3C_ELR_ERRSYN(src) … #define L3C_ELR_ERRWAY(src) … #define L3C_ELR_AGENTID(src) … #define L3C_ELR_ERRGRP(src) … #define L3C_ELR_OPTYPE(src) … #define L3C_ELR_PADDRHIGH(src) … #define L3C_AELR … #define L3C_BELR … #define L3C_BELR_BANK(src) … struct xgene_edac_dev_ctx { … }; /* * Version 1 of the L3 controller has broken single bit correctable logic for * certain error syndromes. Log them as uncorrectable in that case. */ static bool xgene_edac_l3_promote_to_uc_err(u32 l3cesr, u32 l3celr) { … } static void xgene_edac_l3_check(struct edac_device_ctl_info *edac_dev) { … } static void xgene_edac_l3_hw_init(struct edac_device_ctl_info *edac_dev, bool enable) { … } static ssize_t xgene_edac_l3_inject_ctrl_write(struct file *file, const char __user *data, size_t count, loff_t *ppos) { … } static const struct file_operations xgene_edac_l3_debug_inject_fops = …; static void xgene_edac_l3_create_debugfs_nodes(struct edac_device_ctl_info *edac_dev) { … } static int xgene_edac_l3_add(struct xgene_edac *edac, struct device_node *np, int version) { … } static int xgene_edac_l3_remove(struct xgene_edac_dev_ctx *l3) { … } /* SoC error device */ #define IOBAXIS0TRANSERRINTSTS … #define IOBAXIS0_M_ILLEGAL_ACCESS_MASK … #define IOBAXIS0_ILLEGAL_ACCESS_MASK … #define IOBAXIS0TRANSERRINTMSK … #define IOBAXIS0TRANSERRREQINFOL … #define IOBAXIS0TRANSERRREQINFOH … #define REQTYPE_RD(src) … #define ERRADDRH_RD(src) … #define IOBAXIS1TRANSERRINTSTS … #define IOBAXIS1TRANSERRINTMSK … #define IOBAXIS1TRANSERRREQINFOL … #define IOBAXIS1TRANSERRREQINFOH … #define IOBPATRANSERRINTSTS … #define IOBPA_M_REQIDRAM_CORRUPT_MASK … #define IOBPA_REQIDRAM_CORRUPT_MASK … #define IOBPA_M_TRANS_CORRUPT_MASK … #define IOBPA_TRANS_CORRUPT_MASK … #define IOBPA_M_WDATA_CORRUPT_MASK … #define IOBPA_WDATA_CORRUPT_MASK … #define IOBPA_M_RDATA_CORRUPT_MASK … #define IOBPA_RDATA_CORRUPT_MASK … #define IOBBATRANSERRINTSTS … #define M_ILLEGAL_ACCESS_MASK … #define ILLEGAL_ACCESS_MASK … #define M_WIDRAM_CORRUPT_MASK … #define WIDRAM_CORRUPT_MASK … #define M_RIDRAM_CORRUPT_MASK … #define RIDRAM_CORRUPT_MASK … #define M_TRANS_CORRUPT_MASK … #define TRANS_CORRUPT_MASK … #define M_WDATA_CORRUPT_MASK … #define WDATA_CORRUPT_MASK … #define M_RBM_POISONED_REQ_MASK … #define RBM_POISONED_REQ_MASK … #define M_XGIC_POISONED_REQ_MASK … #define XGIC_POISONED_REQ_MASK … #define M_WRERR_RESP_MASK … #define WRERR_RESP_MASK … #define IOBBATRANSERRREQINFOL … #define IOBBATRANSERRREQINFOH … #define REQTYPE_F2_RD(src) … #define ERRADDRH_F2_RD(src) … #define IOBBATRANSERRCSWREQID … #define XGICTRANSERRINTSTS … #define M_WR_ACCESS_ERR_MASK … #define WR_ACCESS_ERR_MASK … #define M_RD_ACCESS_ERR_MASK … #define RD_ACCESS_ERR_MASK … #define XGICTRANSERRINTMSK … #define XGICTRANSERRREQINFO … #define REQTYPE_MASK … #define ERRADDR_RD(src) … #define GLBL_ERR_STS … #define MDED_ERR_MASK … #define DED_ERR_MASK … #define MSEC_ERR_MASK … #define SEC_ERR_MASK … #define GLBL_SEC_ERRL … #define GLBL_SEC_ERRH … #define GLBL_MSEC_ERRL … #define GLBL_MSEC_ERRH … #define GLBL_DED_ERRL … #define GLBL_DED_ERRLMASK … #define GLBL_DED_ERRH … #define GLBL_DED_ERRHMASK … #define GLBL_MDED_ERRL … #define GLBL_MDED_ERRLMASK … #define GLBL_MDED_ERRH … #define GLBL_MDED_ERRHMASK … /* IO Bus Registers */ #define RBCSR … #define STICKYERR_MASK … #define RBEIR … #define AGENT_OFFLINE_ERR_MASK … #define UNIMPL_RBPAGE_ERR_MASK … #define WORD_ALIGNED_ERR_MASK … #define PAGE_ACCESS_ERR_MASK … #define WRITE_ACCESS_MASK … static const char * const soc_mem_err_v1[] = …; static void xgene_edac_iob_gic_report(struct edac_device_ctl_info *edac_dev) { … } static void xgene_edac_rb_report(struct edac_device_ctl_info *edac_dev) { … } static void xgene_edac_pa_report(struct edac_device_ctl_info *edac_dev) { … } static void xgene_edac_soc_check(struct edac_device_ctl_info *edac_dev) { … } static void xgene_edac_soc_hw_init(struct edac_device_ctl_info *edac_dev, bool enable) { … } static int xgene_edac_soc_add(struct xgene_edac *edac, struct device_node *np, int version) { … } static int xgene_edac_soc_remove(struct xgene_edac_dev_ctx *soc) { … } static irqreturn_t xgene_edac_isr(int irq, void *dev_id) { … } static int xgene_edac_probe(struct platform_device *pdev) { … } static void xgene_edac_remove(struct platform_device *pdev) { … } static const struct of_device_id xgene_edac_of_match[] = …; MODULE_DEVICE_TABLE(of, xgene_edac_of_match); static struct platform_driver xgene_edac_driver = …; static int __init xgene_edac_init(void) { … } module_init(…) …; static void __exit xgene_edac_exit(void) { … } module_exit(xgene_edac_exit); MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; module_param(edac_op_state, int, 0444); MODULE_PARM_DESC(…) …;
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