/* * AMD64 class Memory Controller kernel module * * Copyright (c) 2009 SoftwareBitMaker. * Copyright (c) 2009-15 Advanced Micro Devices, Inc. * * This file may be distributed under the terms of the * GNU General Public License. */ #include <linux/module.h> #include <linux/ctype.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/pci_ids.h> #include <linux/slab.h> #include <linux/mmzone.h> #include <linux/edac.h> #include <linux/bitfield.h> #include <asm/cpu_device_id.h> #include <asm/msr.h> #include "edac_module.h" #include "mce_amd.h" #define amd64_info(fmt, arg...) … #define amd64_warn(fmt, arg...) … #define amd64_err(fmt, arg...) … #define amd64_mc_warn(mci, fmt, arg...) … #define amd64_mc_err(mci, fmt, arg...) … /* * Throughout the comments in this code, the following terms are used: * * SysAddr, DramAddr, and InputAddr * * These terms come directly from the amd64 documentation * (AMD publication #26094). They are defined as follows: * * SysAddr: * This is a physical address generated by a CPU core or a device * doing DMA. If generated by a CPU core, a SysAddr is the result of * a virtual to physical address translation by the CPU core's address * translation mechanism (MMU). * * DramAddr: * A DramAddr is derived from a SysAddr by subtracting an offset that * depends on which node the SysAddr maps to and whether the SysAddr * is within a range affected by memory hoisting. The DRAM Base * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers * determine which node a SysAddr maps to. * * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr * is within the range of addresses specified by this register, then * a value x from the DHAR is subtracted from the SysAddr to produce a * DramAddr. Here, x represents the base address for the node that * the SysAddr maps to plus an offset due to memory hoisting. See * section 3.4.8 and the comments in amd64_get_dram_hole_info() and * sys_addr_to_dram_addr() below for more information. * * If the SysAddr is not affected by the DHAR then a value y is * subtracted from the SysAddr to produce a DramAddr. Here, y is the * base address for the node that the SysAddr maps to. See section * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more * information. * * InputAddr: * A DramAddr is translated to an InputAddr before being passed to the * memory controller for the node that the DramAddr is associated * with. The memory controller then maps the InputAddr to a csrow. * If node interleaving is not in use, then the InputAddr has the same * value as the DramAddr. Otherwise, the InputAddr is produced by * discarding the bits used for node interleaving from the DramAddr. * See section 3.4.4 for more information. * * The memory controller for a given node uses its DRAM CS Base and * DRAM CS Mask registers to map an InputAddr to a csrow. See * sections 3.5.4 and 3.5.5 for more information. */ #define EDAC_MOD_STR … /* Extended Model from CPUID, for CPU Revision numbers */ #define K8_REV_D … #define K8_REV_E … #define K8_REV_F … /* Hardware limit on ChipSelect rows per MC and processors per system */ #define NUM_CHIPSELECTS … #define DRAM_RANGES … #define NUM_CONTROLLERS … #define ON … #define OFF … /* * PCI-defined configuration space registers */ #define PCI_DEVICE_ID_AMD_15H_NB_F1 … #define PCI_DEVICE_ID_AMD_15H_NB_F2 … #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 … #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 … #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 … #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 … #define PCI_DEVICE_ID_AMD_16H_NB_F1 … #define PCI_DEVICE_ID_AMD_16H_NB_F2 … #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 … #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 … /* * Function 1 - Address Map */ #define DRAM_BASE_LO … #define DRAM_LIMIT_LO … /* * F15 M30h D18F1x2[1C:00] */ #define DRAM_CONT_BASE … #define DRAM_CONT_LIMIT … /* * F15 M30h D18F1x2[4C:40] */ #define DRAM_CONT_HIGH_OFF … #define dram_rw(pvt, i) … #define dram_intlv_sel(pvt, i) … #define dram_dst_node(pvt, i) … #define DHAR … #define dhar_mem_hoist_valid(pvt) … #define dhar_base(pvt) … #define k8_dhar_offset(pvt) … /* NOTE: Extra mask bit vs K8 */ #define f10_dhar_offset(pvt) … #define DCT_CFG_SEL … #define DRAM_LOCAL_NODE_BASE … #define DRAM_LOCAL_NODE_LIM … #define DRAM_BASE_HI … #define DRAM_LIMIT_HI … /* * Function 2 - DRAM controller */ #define DCSB0 … #define DCSB1 … #define DCSB_CS_ENABLE … #define DCSM0 … #define DCSM1 … #define csrow_enabled(i, dct, pvt) … #define csrow_sec_enabled(i, dct, pvt) … #define DRAM_CONTROL … #define DBAM0 … #define DBAM1 … /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ #define DBAM_DIMM(i, reg) … #define DBAM_MAX_VALUE … #define DCLR0 … #define DCLR1 … #define REVE_WIDTH_128 … #define WIDTH_128 … #define DCHR0 … #define DCHR1 … #define DDR3_MODE … #define DCT_SEL_LO … #define dct_high_range_enabled(pvt) … #define dct_interleave_enabled(pvt) … #define dct_ganging_enabled(pvt) … #define dct_data_intlv_enabled(pvt) … #define dct_memory_cleared(pvt) … #define SWAP_INTLV_REG … #define DCT_SEL_HI … #define F15H_M60H_SCRCTRL … /* * Function 3 - Misc Control */ #define NBCTL … #define NBCFG … #define NBCFG_CHIPKILL … #define NBCFG_ECC_ENABLE … /* F3x48: NBSL */ #define F10_NBSL_EXT_ERR_ECC … #define NBSL_PP_OBS … #define SCRCTRL … #define F10_ONLINE_SPARE … #define online_spare_swap_done(pvt, c) … #define online_spare_bad_dramcs(pvt, c) … #define F10_NB_ARRAY_ADDR … #define F10_NB_ARRAY_DRAM … /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ #define SET_NB_ARRAY_ADDR(section) … #define F10_NB_ARRAY_DATA … #define F10_NB_ARR_ECC_WR_REQ … #define SET_NB_DRAM_INJECTION_WRITE(inj) … #define SET_NB_DRAM_INJECTION_READ(inj) … #define NBCAP … #define NBCAP_CHIPKILL … #define NBCAP_SECDED … #define NBCAP_DCT_DUAL … #define EXT_NB_MCA_CFG … /* MSRs */ #define MSR_MCGCTL_NBE … /* F17h */ /* F0: */ #define DF_DHAR … /* UMC CH register offsets */ #define UMCCH_BASE_ADDR … #define UMCCH_BASE_ADDR_SEC … #define UMCCH_ADDR_MASK … #define UMCCH_ADDR_MASK_SEC … #define UMCCH_ADDR_MASK_SEC_DDR5 … #define UMCCH_DIMM_CFG … #define UMCCH_DIMM_CFG_DDR5 … #define UMCCH_UMC_CFG … #define UMCCH_SDP_CTRL … #define UMCCH_ECC_CTRL … #define UMCCH_UMC_CAP_HI … /* UMC CH bitfields */ #define UMC_ECC_CHIPKILL_CAP … #define UMC_ECC_ENABLED … #define UMC_SDP_INIT … /* Error injection control structure */ struct error_injection { … }; /* low and high part of PCI config space regs */ struct reg_pair { … }; /* * See F1x[1, 0][7C:40] DRAM Base/Limit Registers */ struct dram_range { … }; /* A DCT chip selects collection */ struct chip_select { … }; struct amd64_umc { … }; struct amd64_family_flags { … }; struct amd64_pvt { … }; enum err_codes { … }; struct err_info { … }; static inline u32 get_umc_base(u8 channel) { … } static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i) { … } static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i) { … } static inline u16 extract_syndrome(u64 status) { … } static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt) { … } /* * per-node ECC settings descriptor */ struct ecc_settings { … }; /* * Each of the PCI Device IDs types have their own set of hardware accessor * functions and per device encoding/decoding logic. */ struct low_ops { … }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, u32 *val, const char *func); int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, u32 val, const char *func); #define amd64_read_pci_cfg(pdev, offset, val) … #define amd64_write_pci_cfg(pdev, offset, val) … #define to_mci(k) … /* Injection helpers */ static inline void disable_caches(void *dummy) { … } static inline void enable_caches(void *dummy) { … } static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i) { … } static inline u8 dhar_valid(struct amd64_pvt *pvt) { … } static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt) { … }
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