/* SPDX-License-Identifier: GPL-2.0-only */ /* * (c) 2003-2006 Advanced Micro Devices, Inc. */ struct powernow_k8_data { … }; /* processor's cpuid instruction support */ #define CPUID_PROCESSOR_SIGNATURE … #define CPUID_XFAM … #define CPUID_XFAM_K8 … #define CPUID_XMOD … #define CPUID_XMOD_REV_MASK … #define CPUID_XFAM_10H … #define CPUID_USE_XFAM_XMOD … #define CPUID_GET_MAX_CAPABILITIES … #define CPUID_FREQ_VOLT_CAPABILITIES … #define P_STATE_TRANSITION_CAPABLE … /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */ /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */ /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */ /* the register number is placed in ecx, and the data is returned in edx:eax. */ #define MSR_FIDVID_CTL … #define MSR_FIDVID_STATUS … /* Field definitions within the FID VID Low Control MSR : */ #define MSR_C_LO_INIT_FID_VID … #define MSR_C_LO_NEW_VID … #define MSR_C_LO_NEW_FID … #define MSR_C_LO_VID_SHIFT … /* Field definitions within the FID VID High Control MSR : */ #define MSR_C_HI_STP_GNT_TO … /* Field definitions within the FID VID Low Status MSR : */ #define MSR_S_LO_CHANGE_PENDING … #define MSR_S_LO_MAX_RAMP_VID … #define MSR_S_LO_MAX_FID … #define MSR_S_LO_START_FID … #define MSR_S_LO_CURRENT_FID … /* Field definitions within the FID VID High Status MSR : */ #define MSR_S_HI_MIN_WORKING_VID … #define MSR_S_HI_MAX_WORKING_VID … #define MSR_S_HI_START_VID … #define MSR_S_HI_CURRENT_VID … #define MSR_C_HI_STP_GNT_BENIGN … /* * There are restrictions frequencies have to follow: * - only 1 entry in the low fid table ( <=1.4GHz ) * - lowest entry in the high fid table must be >= 2 * the entry in the * low fid table * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry * in the low fid table * - the parts can only step at <= 200 MHz intervals, odd fid values are * supported in revision G and later revisions. * - lowest frequency must be >= interprocessor hypertransport link speed * (only applies to MP systems obviously) */ /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */ #define LO_FID_TABLE_TOP … #define HI_FID_TABLE_BOTTOM … #define LO_VCOFREQ_TABLE_TOP … #define HI_VCOFREQ_TABLE_BOTTOM … #define MIN_FREQ_RESOLUTION … #define MAX_FID … #define LEAST_VID … #define MIN_FREQ … #define MAX_FREQ … #define INVALID_FID_MASK … #define INVALID_VID_MASK … #define VID_OFF … #define STOP_GRANT_5NS … #define PLL_LOCK_CONVERSION … #define MAXIMUM_VID_STEPS … #define VST_UNITS_20US … /* * Most values of interest are encoded in a single field of the _PSS * entries: the "control" value. */ #define IRT_SHIFT … #define RVO_SHIFT … #define EXT_TYPE_SHIFT … #define PLL_L_SHIFT … #define MVS_SHIFT … #define VST_SHIFT … #define VID_SHIFT … #define IRT_MASK … #define RVO_MASK … #define EXT_TYPE_MASK … #define PLL_L_MASK … #define MVS_MASK … #define VST_MASK … #define VID_MASK … #define FID_MASK … #define EXT_VID_MASK … #define EXT_FID_MASK … /* * Version 1.4 of the PSB table. This table is constructed by BIOS and is * to tell the OS's power management driver which VIDs and FIDs are * supported by this particular processor. * If the data in the PSB / PST is wrong, then this driver will program the * wrong values into hardware, which is very likely to lead to a crash. */ #define PSB_ID_STRING … #define PSB_ID_STRING_LEN … #define PSB_VERSION_1_4 … struct psb_s { … }; /* Pairs of fid/vid values are appended to the version 1.4 PSB table. */ struct pst_s { … }; static int core_voltage_pre_transition(struct powernow_k8_data *data, u32 reqvid, u32 regfid); static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid); static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid); static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index); static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
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