linux/drivers/clk/bcm/clk-iproc-pll.c

// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2014 Broadcom Corporation

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/clkdev.h>
#include <linux/of_address.h>
#include <linux/delay.h>

#include "clk-iproc.h"

#define PLL_VCO_HIGH_SHIFT …
#define PLL_VCO_LOW_SHIFT …

/*
 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
 */
#define PLL_USER_MODE …

/* number of delay loops waiting for PLL to lock */
#define LOCK_DELAY …

/* number of VCO frequency bands */
#define NUM_FREQ_BANDS …

#define NUM_KP_BANDS …
enum kp_band { … };

static const unsigned int kp_table[NUM_KP_BANDS][NUM_FREQ_BANDS] = …;

static const unsigned long ref_freq_table[NUM_FREQ_BANDS][2] = …;

enum vco_freq_range { … };

struct iproc_pll { … };

struct iproc_clk { … };

#define to_iproc_clk(hw) …

static int pll_calc_param(unsigned long target_rate,
			unsigned long parent_rate,
			struct iproc_pll_vco_param *vco_out)
{ … }

/*
 * Based on the target frequency, find a match from the VCO frequency parameter
 * table and return its index
 */
static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate)
{ … }

static int get_kp(unsigned long ref_freq, enum kp_band kp_index)
{ … }

static int pll_wait_for_lock(struct iproc_pll *pll)
{ … }

static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base,
			    const u32 offset, u32 val)
{ … }

static void __pll_disable(struct iproc_pll *pll)
{ … }

static int __pll_enable(struct iproc_pll *pll)
{ … }

static void __pll_put_in_reset(struct iproc_pll *pll)
{ … }

static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
				  unsigned int ka, unsigned int ki)
{ … }

/*
 * Determines if the change to be applied to the PLL is minor (just an update
 * or the fractional divider). If so, then we can avoid going through a
 * disruptive reset and lock sequence.
 */
static bool pll_fractional_change_only(struct iproc_pll *pll,
				       struct iproc_pll_vco_param *vco)
{ … }

static int pll_set_rate(struct iproc_clk *clk, struct iproc_pll_vco_param *vco,
			unsigned long parent_rate)
{ … }

static int iproc_pll_enable(struct clk_hw *hw)
{ … }

static void iproc_pll_disable(struct clk_hw *hw)
{ … }

static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
					   unsigned long parent_rate)
{ … }

static int iproc_pll_determine_rate(struct clk_hw *hw,
		struct clk_rate_request *req)
{ … }

static int iproc_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{ … }

static const struct clk_ops iproc_pll_ops = …;

static int iproc_clk_enable(struct clk_hw *hw)
{ … }

static void iproc_clk_disable(struct clk_hw *hw)
{ … }

static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{ … }

static int iproc_clk_determine_rate(struct clk_hw *hw,
		struct clk_rate_request *req)
{ … }

static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{ … }

static const struct clk_ops iproc_clk_ops = …;

/*
 * Some PLLs require the PLL SW override bit to be set before changes can be
 * applied to the PLL
 */
static void iproc_pll_sw_cfg(struct iproc_pll *pll)
{ … }

void iproc_pll_clk_setup(struct device_node *node,
			 const struct iproc_pll_ctrl *pll_ctrl,
			 const struct iproc_pll_vco_param *vco,
			 unsigned int num_vco_entries,
			 const struct iproc_clk_ctrl *clk_ctrl,
			 unsigned int num_clks)
{ … }