/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (c) 2015, The Linux Foundation. All rights reserved. */ #ifndef LINUX_MMC_CQHCI_H #define LINUX_MMC_CQHCI_H #include <linux/compiler.h> #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/spinlock_types.h> #include <linux/types.h> #include <linux/completion.h> #include <linux/wait.h> #include <linux/irqreturn.h> #include <asm/io.h> /* registers */ /* version */ #define CQHCI_VER … #define CQHCI_VER_MAJOR(x) … #define CQHCI_VER_MINOR1(x) … #define CQHCI_VER_MINOR2(x) … /* capabilities */ #define CQHCI_CAP … #define CQHCI_CAP_CS … #define CQHCI_CAP_ITCFMUL … #define CQHCI_ITCFMUL(x) … /* configuration */ #define CQHCI_CFG … #define CQHCI_DCMD … #define CQHCI_TASK_DESC_SZ … #define CQHCI_CRYPTO_GENERAL_ENABLE … #define CQHCI_ENABLE … /* control */ #define CQHCI_CTL … #define CQHCI_CLEAR_ALL_TASKS … #define CQHCI_HALT … /* interrupt status */ #define CQHCI_IS … #define CQHCI_IS_HAC … #define CQHCI_IS_TCC … #define CQHCI_IS_RED … #define CQHCI_IS_TCL … #define CQHCI_IS_GCE … #define CQHCI_IS_ICCE … #define CQHCI_IS_MASK … /* interrupt status enable */ #define CQHCI_ISTE … /* interrupt signal enable */ #define CQHCI_ISGE … /* interrupt coalescing */ #define CQHCI_IC … #define CQHCI_IC_ENABLE … #define CQHCI_IC_RESET … #define CQHCI_IC_ICCTHWEN … #define CQHCI_IC_ICCTH(x) … #define CQHCI_IC_ICTOVALWEN … #define CQHCI_IC_ICTOVAL(x) … /* task list base address */ #define CQHCI_TDLBA … /* task list base address upper */ #define CQHCI_TDLBAU … /* door-bell */ #define CQHCI_TDBR … /* task completion notification */ #define CQHCI_TCN … /* device queue status */ #define CQHCI_DQS … /* device pending tasks */ #define CQHCI_DPT … /* task clear */ #define CQHCI_TCLR … /* task descriptor processing error */ #define CQHCI_TDPE … /* send status config 1 */ #define CQHCI_SSC1 … #define CQHCI_SSC1_CBC_MASK … /* send status config 2 */ #define CQHCI_SSC2 … /* response for dcmd */ #define CQHCI_CRDCT … /* response mode error mask */ #define CQHCI_RMEM … /* task error info */ #define CQHCI_TERRI … #define CQHCI_TERRI_C_INDEX(x) … #define CQHCI_TERRI_C_TASK(x) … #define CQHCI_TERRI_C_VALID(x) … #define CQHCI_TERRI_D_INDEX(x) … #define CQHCI_TERRI_D_TASK(x) … #define CQHCI_TERRI_D_VALID(x) … /* command response index */ #define CQHCI_CRI … /* command response argument */ #define CQHCI_CRA … /* crypto capabilities */ #define CQHCI_CCAP … #define CQHCI_CRYPTOCAP … #define CQHCI_INT_ALL … #define CQHCI_IC_DEFAULT_ICCTH … #define CQHCI_IC_DEFAULT_ICTOVAL … /* attribute fields */ #define CQHCI_VALID(x) … #define CQHCI_END(x) … #define CQHCI_INT(x) … #define CQHCI_ACT(x) … /* data command task descriptor fields */ #define CQHCI_FORCED_PROG(x) … #define CQHCI_CONTEXT(x) … #define CQHCI_DATA_TAG(x) … #define CQHCI_DATA_DIR(x) … #define CQHCI_PRIORITY(x) … #define CQHCI_QBAR(x) … #define CQHCI_REL_WRITE(x) … #define CQHCI_BLK_COUNT(x) … #define CQHCI_BLK_ADDR(x) … /* direct command task descriptor fields */ #define CQHCI_CMD_INDEX(x) … #define CQHCI_CMD_TIMING(x) … #define CQHCI_RESP_TYPE(x) … /* crypto task descriptor fields (for bits 64-127 of task descriptor) */ #define CQHCI_CRYPTO_ENABLE_BIT … #define CQHCI_CRYPTO_KEYSLOT(x) … /* transfer descriptor fields */ #define CQHCI_DAT_LENGTH(x) … #define CQHCI_DAT_ADDR_LO(x) … #define CQHCI_DAT_ADDR_HI(x) … /* CCAP - Crypto Capability 100h */ cqhci_crypto_capabilities; enum cqhci_crypto_key_size { … }; enum cqhci_crypto_alg { … }; /* x-CRYPTOCAP - Crypto Capability X */ cqhci_crypto_cap_entry; #define CQHCI_CRYPTO_CONFIGURATION_ENABLE … #define CQHCI_CRYPTO_KEY_MAX_SIZE … /* x-CRYPTOCFG - Crypto Configuration X */ cqhci_crypto_cfg_entry; struct cqhci_host_ops; struct mmc_host; struct mmc_request; struct cqhci_slot; struct cqhci_host { … }; struct cqhci_host_ops { … }; static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg) { … } static inline u32 cqhci_readl(struct cqhci_host *host, int reg) { … } struct platform_device; irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error, int data_error); int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64); struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev); int cqhci_deactivate(struct mmc_host *mmc); void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, bool dma64); static inline int cqhci_suspend(struct mmc_host *mmc) { … } int cqhci_resume(struct mmc_host *mmc); #endif
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