// SPDX-License-Identifier: GPL-2.0 /* * sdhci-pci-arasan.c - Driver for Arasan PCI Controller with * integrated phy. * * Copyright (C) 2017 Arasan Chip Systems Inc. * * Author: Atul Garg <[email protected]> */ #include <linux/pci.h> #include <linux/delay.h> #include "sdhci.h" #include "sdhci-pci.h" /* Extra registers for Arasan SD/SDIO/MMC Host Controller with PHY */ #define PHY_ADDR_REG … #define PHY_DAT_REG … #define PHY_WRITE … #define PHY_BUSY … #define DATA_MASK … /* PHY Specific Registers */ #define DLL_STATUS … #define IPAD_CTRL1 … #define IPAD_CTRL2 … #define IPAD_STS … #define IOREN_CTRL1 … #define IOREN_CTRL2 … #define IOPU_CTRL1 … #define IOPU_CTRL2 … #define ITAP_DELAY … #define OTAP_DELAY … #define STRB_SEL … #define CLKBUF_SEL … #define MODE_CTRL … #define DLL_TRIM … #define CMD_CTRL … #define DATA_CTRL … #define STRB_CTRL … #define CLK_CTRL … #define PHY_CTRL … #define DLL_ENBL … #define RTRIM_EN … #define PDB_ENBL … #define RETB_ENBL … #define ODEN_CMD … #define ODEN_DAT … #define REN_STRB … #define REN_CMND … #define REN_DATA … #define PU_CMD … #define PU_DAT … #define ITAPDLY_EN … #define OTAPDLY_EN … #define OD_REL_CMD … #define OD_REL_DAT … #define DLLTRM_ICP … #define PDB_CMND … #define PDB_DATA … #define PDB_STRB … #define PDB_CLOCK … #define CALDONE_MASK … #define DLL_RDY_MASK … #define MAX_CLK_BUF … /* Mode Controls */ #define ENHSTRB_MODE … #define HS400_MODE … #define LEGACY_MODE … #define DDR50_MODE … /* * Controller has no specific bits for HS200/HS. * Used BIT(4), BIT(5) for software programming. */ #define HS200_MODE … #define HISPD_MODE … #define OTAPDLY(x) … #define ITAPDLY(x) … #define FREQSEL(x) … #define IOPAD(x, y) … /* Arasan private data */ struct arasan_host { … }; static int arasan_phy_addr_poll(struct sdhci_host *host, u32 offset, u32 mask) { … } static int arasan_phy_write(struct sdhci_host *host, u8 data, u8 offset) { … } static int arasan_phy_read(struct sdhci_host *host, u8 offset, u8 *data) { … } static int arasan_phy_sts_poll(struct sdhci_host *host, u32 offset, u32 mask) { … } /* Initialize the Arasan PHY */ static int arasan_phy_init(struct sdhci_host *host) { … } /* Set Arasan PHY for different modes */ static int arasan_phy_set(struct sdhci_host *host, u8 mode, u8 otap, u8 drv_type, u8 itap, u8 trim, u8 clk) { … } static int arasan_select_phy_clock(struct sdhci_host *host) { … } static int arasan_pci_probe_slot(struct sdhci_pci_slot *slot) { … } static void arasan_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) { … } static const struct sdhci_ops arasan_sdhci_pci_ops = …; const struct sdhci_pci_fixes sdhci_arasan = …;
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