/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Synopsys DesignWare Multimedia Card Interface driver * (Based on NXP driver for lpc 31xx) * * Copyright (C) 2009 NXP Semiconductors * Copyright (C) 2009, 2010 Imagination Technologies Ltd. */ #ifndef _DW_MMC_H_ #define _DW_MMC_H_ #include <linux/scatterlist.h> #include <linux/mmc/core.h> #include <linux/dmaengine.h> #include <linux/reset.h> #include <linux/fault-inject.h> #include <linux/hrtimer.h> #include <linux/interrupt.h> #include <linux/workqueue.h> enum dw_mci_state { … }; enum { … }; enum dw_mci_cookie { … }; struct mmc_data; enum { … }; struct dw_mci_dma_slave { … }; /** * struct dw_mci - MMC controller state shared between all slots * @lock: Spinlock protecting the queue and associated data. * @irq_lock: Spinlock protecting the INTMASK setting. * @regs: Pointer to MMIO registers. * @fifo_reg: Pointer to MMIO registers for data FIFO * @sg: Scatterlist entry currently being processed by PIO code, if any. * @sg_miter: PIO mapping scatterlist iterator. * @mrq: The request currently being processed on @slot, * or NULL if the controller is idle. * @cmd: The command currently being sent to the card, or NULL. * @data: The data currently being transferred, or NULL if no data * transfer is in progress. * @stop_abort: The command currently prepared for stoping transfer. * @prev_blksz: The former transfer blksz record. * @timing: Record of current ios timing. * @use_dma: Which DMA channel is in use for the current transfer, zero * denotes PIO mode. * @using_dma: Whether DMA is in use for the current transfer. * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. * @sg_dma: Bus address of DMA buffer. * @sg_cpu: Virtual address of DMA buffer. * @dma_ops: Pointer to platform-specific DMA callbacks. * @cmd_status: Snapshot of SR taken upon completion of the current * @ring_size: Buffer size for idma descriptors. * command. Only valid when EVENT_CMD_COMPLETE is pending. * @dms: structure of slave-dma private data. * @phy_regs: physical address of controller's register map * @data_status: Snapshot of SR taken upon completion of the current * data transfer. Only valid when EVENT_DATA_COMPLETE or * EVENT_DATA_ERROR is pending. * @stop_cmdr: Value to be loaded into CMDR when the stop command is * to be sent. * @dir_status: Direction of current transfer. * @bh_work: Work running the request state machine. * @pending_events: Bitmask of events flagged by the interrupt handler * to be processed by bh work. * @completed_events: Bitmask of events which the state machine has * processed. * @state: BH work state. * @queue: List of slots waiting for access to the controller. * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus * rate and timeout calculations. * @current_speed: Configured rate of the controller. * @minimum_speed: Stored minimum rate of the controller. * @fifoth_val: The value of FIFOTH register. * @verid: Denote Version ID. * @dev: Device associated with the MMC controller. * @pdata: Platform data associated with the MMC controller. * @drv_data: Driver specific data for identified variant of the controller * @priv: Implementation defined private data. * @biu_clk: Pointer to bus interface unit clock instance. * @ciu_clk: Pointer to card interface unit clock instance. * @slot: Slots sharing this MMC controller. * @fifo_depth: depth of FIFO. * @data_addr_override: override fifo reg offset with this value. * @wm_aligned: force fifo watermark equal with data length in PIO mode. * Set as true if alignment is needed. * @data_shift: log2 of FIFO item size. * @part_buf_start: Start index in part_buf. * @part_buf_count: Bytes of partial data in part_buf. * @part_buf: Simple buffer for partial fifo reads/writes. * @push_data: Pointer to FIFO push function. * @pull_data: Pointer to FIFO pull function. * @quirks: Set of quirks that apply to specific versions of the IP. * @vqmmc_enabled: Status of vqmmc, should be true or false. * @irq_flags: The flags to be passed to request_irq. * @irq: The irq value to be passed to request_irq. * @sdio_id0: Number of slot0 in the SDIO interrupt registers. * @cmd11_timer: Timer for SD3.0 voltage switch over scheme. * @cto_timer: Timer for broken command transfer over scheme. * @dto_timer: Timer for broken data transfer over scheme. * * Locking * ======= * * @lock is a softirq-safe spinlock protecting @queue as well as * @slot, @mrq and @state. These must always be updated * at the same time while holding @lock. * The @mrq field of struct dw_mci_slot is also protected by @lock, * and must always be written at the same time as the slot is added to * @queue. * * @irq_lock is an irq-safe spinlock protecting the INTMASK register * to allow the interrupt handler to modify it directly. Held for only long * enough to read-modify-write INTMASK and no other locks are grabbed when * holding this one. * * @pending_events and @completed_events are accessed using atomic bit * operations, so they don't need any locking. * * None of the fields touched by the interrupt handler need any * locking. However, ordering is important: Before EVENT_DATA_ERROR or * EVENT_DATA_COMPLETE is set in @pending_events, all data-related * interrupts must be disabled and @data_status updated with a * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the * CMDRDY interrupt must be disabled and @cmd_status updated with a * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the * bytes_xfered field of @data must be written. This is ensured by * using barriers. */ struct dw_mci { … }; /* DMA ops for Internal/External DMAC interface */ struct dw_mci_dma_ops { … }; struct dma_pdata; /* Board platform data */ struct dw_mci_board { … }; /* Support for longer data read timeout */ #define DW_MMC_QUIRK_EXTENDED_TMOUT … #define DW_MMC_240A … #define DW_MMC_280A … #define SDMMC_CTRL … #define SDMMC_PWREN … #define SDMMC_CLKDIV … #define SDMMC_CLKSRC … #define SDMMC_CLKENA … #define SDMMC_TMOUT … #define SDMMC_CTYPE … #define SDMMC_BLKSIZ … #define SDMMC_BYTCNT … #define SDMMC_INTMASK … #define SDMMC_CMDARG … #define SDMMC_CMD … #define SDMMC_RESP0 … #define SDMMC_RESP1 … #define SDMMC_RESP2 … #define SDMMC_RESP3 … #define SDMMC_MINTSTS … #define SDMMC_RINTSTS … #define SDMMC_STATUS … #define SDMMC_FIFOTH … #define SDMMC_CDETECT … #define SDMMC_WRTPRT … #define SDMMC_GPIO … #define SDMMC_TCBCNT … #define SDMMC_TBBCNT … #define SDMMC_DEBNCE … #define SDMMC_USRID … #define SDMMC_VERID … #define SDMMC_HCON … #define SDMMC_UHS_REG … #define SDMMC_RST_N … #define SDMMC_BMOD … #define SDMMC_PLDMND … #define SDMMC_DBADDR … #define SDMMC_IDSTS … #define SDMMC_IDINTEN … #define SDMMC_DSCADDR … #define SDMMC_BUFADDR … #define SDMMC_CDTHRCTL … #define SDMMC_UHS_REG_EXT … #define SDMMC_DDR_REG … #define SDMMC_ENABLE_SHIFT … #define SDMMC_DATA(x) … /* * Registers to support idmac 64-bit address mode */ #define SDMMC_DBADDRL … #define SDMMC_DBADDRU … #define SDMMC_IDSTS64 … #define SDMMC_IDINTEN64 … #define SDMMC_DSCADDRL … #define SDMMC_DSCADDRU … #define SDMMC_BUFADDRL … #define SDMMC_BUFADDRU … /* * Data offset is difference according to Version * Lower than 2.40a : data register offest is 0x100 */ #define DATA_OFFSET … #define DATA_240A_OFFSET … /* shift bit field */ #define _SBF(f, v) … /* Control register defines */ #define SDMMC_CTRL_USE_IDMAC … #define SDMMC_CTRL_CEATA_INT_EN … #define SDMMC_CTRL_SEND_AS_CCSD … #define SDMMC_CTRL_SEND_CCSD … #define SDMMC_CTRL_ABRT_READ_DATA … #define SDMMC_CTRL_SEND_IRQ_RESP … #define SDMMC_CTRL_READ_WAIT … #define SDMMC_CTRL_DMA_ENABLE … #define SDMMC_CTRL_INT_ENABLE … #define SDMMC_CTRL_DMA_RESET … #define SDMMC_CTRL_FIFO_RESET … #define SDMMC_CTRL_RESET … /* Clock Enable register defines */ #define SDMMC_CLKEN_LOW_PWR … #define SDMMC_CLKEN_ENABLE … /* time-out register defines */ #define SDMMC_TMOUT_DATA(n) … #define SDMMC_TMOUT_DATA_MSK … #define SDMMC_TMOUT_RESP(n) … #define SDMMC_TMOUT_RESP_MSK … /* card-type register defines */ #define SDMMC_CTYPE_8BIT … #define SDMMC_CTYPE_4BIT … #define SDMMC_CTYPE_1BIT … /* Interrupt status & mask register defines */ #define SDMMC_INT_SDIO(n) … #define SDMMC_INT_EBE … #define SDMMC_INT_ACD … #define SDMMC_INT_SBE … #define SDMMC_INT_HLE … #define SDMMC_INT_FRUN … #define SDMMC_INT_HTO … #define SDMMC_INT_VOLT_SWITCH … #define SDMMC_INT_DRTO … #define SDMMC_INT_RTO … #define SDMMC_INT_DCRC … #define SDMMC_INT_RCRC … #define SDMMC_INT_RXDR … #define SDMMC_INT_TXDR … #define SDMMC_INT_DATA_OVER … #define SDMMC_INT_CMD_DONE … #define SDMMC_INT_RESP_ERR … #define SDMMC_INT_CD … #define SDMMC_INT_ERROR … /* Command register defines */ #define SDMMC_CMD_START … #define SDMMC_CMD_USE_HOLD_REG … #define SDMMC_CMD_VOLT_SWITCH … #define SDMMC_CMD_CCS_EXP … #define SDMMC_CMD_CEATA_RD … #define SDMMC_CMD_UPD_CLK … #define SDMMC_CMD_INIT … #define SDMMC_CMD_STOP … #define SDMMC_CMD_PRV_DAT_WAIT … #define SDMMC_CMD_SEND_STOP … #define SDMMC_CMD_STRM_MODE … #define SDMMC_CMD_DAT_WR … #define SDMMC_CMD_DAT_EXP … #define SDMMC_CMD_RESP_CRC … #define SDMMC_CMD_RESP_LONG … #define SDMMC_CMD_RESP_EXP … #define SDMMC_CMD_INDX(n) … /* Status register defines */ #define SDMMC_GET_FCNT(x) … #define SDMMC_STATUS_DMA_REQ … #define SDMMC_STATUS_BUSY … /* FIFOTH register defines */ #define SDMMC_SET_FIFOTH(m, r, t) … /* HCON register defines */ #define DMA_INTERFACE_IDMA … #define DMA_INTERFACE_DWDMA … #define DMA_INTERFACE_GDMA … #define DMA_INTERFACE_NODMA … #define SDMMC_GET_TRANS_MODE(x) … #define SDMMC_GET_SLOT_NUM(x) … #define SDMMC_GET_HDATA_WIDTH(x) … #define SDMMC_GET_ADDR_CONFIG(x) … /* Internal DMAC interrupt defines */ #define SDMMC_IDMAC_INT_AI … #define SDMMC_IDMAC_INT_NI … #define SDMMC_IDMAC_INT_CES … #define SDMMC_IDMAC_INT_DU … #define SDMMC_IDMAC_INT_FBE … #define SDMMC_IDMAC_INT_RI … #define SDMMC_IDMAC_INT_TI … /* Internal DMAC bus mode bits */ #define SDMMC_IDMAC_ENABLE … #define SDMMC_IDMAC_FB … #define SDMMC_IDMAC_SWRESET … /* H/W reset */ #define SDMMC_RST_HWACTIVE … /* Version ID register define */ #define SDMMC_GET_VERID(x) … /* Card read threshold */ #define SDMMC_SET_THLD(v, x) … #define SDMMC_CARD_WR_THR_EN … #define SDMMC_CARD_RD_THR_EN … /* UHS-1 register defines */ #define SDMMC_UHS_DDR … #define SDMMC_UHS_18V … /* DDR register defines */ #define SDMMC_DDR_HS400 … /* Enable shift register defines */ #define SDMMC_ENABLE_PHASE … /* All ctrl reset bits */ #define SDMMC_CTRL_ALL_RESET_FLAGS … /* FIFO register access macros. These should not change the data endian-ness * as they are written to memory to be dealt with by the upper layers */ #define mci_fifo_readw(__reg) … #define mci_fifo_readl(__reg) … #define mci_fifo_readq(__reg) … #define mci_fifo_writew(__value, __reg) … #define mci_fifo_writel(__value, __reg) … #define mci_fifo_writeq(__value, __reg) … /* Register access macros */ #define mci_readl(dev, reg) … #define mci_writel(dev, reg, value) … /* 16-bit FIFO access macros */ #define mci_readw(dev, reg) … #define mci_writew(dev, reg, value) … /* 64-bit FIFO access macros */ #ifdef readq #define mci_readq(dev, reg) … #define mci_writeq(dev, reg, value) … #else /* * Dummy readq implementation for architectures that don't define it. * * We would assume that none of these architectures would configure * the IP block with a 64bit FIFO width, so this code will never be * executed on those machines. Defining these macros here keeps the * rest of the code free from ifdefs. */ #define mci_readq … #define mci_writeq … #define __raw_writeq … #define __raw_readq … #endif extern int dw_mci_probe(struct dw_mci *host); extern void dw_mci_remove(struct dw_mci *host); #ifdef CONFIG_PM extern int dw_mci_runtime_suspend(struct device *device); extern int dw_mci_runtime_resume(struct device *device); #endif /** * struct dw_mci_slot - MMC slot state * @mmc: The mmc_host representing this slot. * @host: The MMC controller this slot is using. * @ctype: Card type for this slot. * @mrq: mmc_request currently being processed or waiting to be * processed, or NULL when the slot is idle. * @queue_node: List node for placing this node in the @queue list of * &struct dw_mci. * @clock: Clock rate configured by set_ios(). Protected by host->lock. * @__clk_old: The last clock value that was requested from core. * Keeping track of this helps us to avoid spamming the console. * @flags: Random state bits associated with the slot. * @id: Number of this slot. * @sdio_id: Number of this slot in the SDIO interrupt registers. */ struct dw_mci_slot { … }; /** * dw_mci driver data - dw-mshc implementation specific driver data. * @caps: mmc subsystem specified capabilities of the controller(s). * @num_caps: number of capabilities specified by @caps. * @common_caps: mmc subsystem specified capabilities applicable to all of * the controllers * @init: early implementation specific initialization. * @set_ios: handle bus specific extensions. * @parse_dt: parse implementation specific device tree properties. * @execute_tuning: implementation specific tuning procedure. * @set_data_timeout: implementation specific timeout. * @get_drto_clks: implementation specific cycle count for data read timeout. * @hw_reset: implementation specific HW reset. * * Provide controller implementation specific extensions. The usage of this * data structure is fully optional and usage of each member in this structure * is optional as well. */ struct dw_mci_drv_data { … }; #endif /* _DW_MMC_H_ */
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