// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2016 Socionext Inc. * Author: Masahiro Yamada <[email protected]> */ #include <linux/bitfield.h> #include <linux/bits.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/mmc/host.h> #include <linux/mmc/mmc.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/reset.h> #include "sdhci-pltfm.h" /* HRS - Host Register Set (specific to Cadence) */ #define SDHCI_CDNS_HRS04 … #define SDHCI_CDNS_HRS04_ACK … #define SDHCI_CDNS_HRS04_RD … #define SDHCI_CDNS_HRS04_WR … #define SDHCI_CDNS_HRS04_RDATA … #define SDHCI_CDNS_HRS04_WDATA … #define SDHCI_CDNS_HRS04_ADDR … #define SDHCI_CDNS_HRS06 … #define SDHCI_CDNS_HRS06_TUNE_UP … #define SDHCI_CDNS_HRS06_TUNE … #define SDHCI_CDNS_HRS06_MODE … #define SDHCI_CDNS_HRS06_MODE_SD … #define SDHCI_CDNS_HRS06_MODE_MMC_SDR … #define SDHCI_CDNS_HRS06_MODE_MMC_DDR … #define SDHCI_CDNS_HRS06_MODE_MMC_HS200 … #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 … #define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES … /* SRS - Slot Register Set (SDHCI-compatible) */ #define SDHCI_CDNS_SRS_BASE … /* PHY */ #define SDHCI_CDNS_PHY_DLY_SD_HS … #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT … #define SDHCI_CDNS_PHY_DLY_UHS_SDR12 … #define SDHCI_CDNS_PHY_DLY_UHS_SDR25 … #define SDHCI_CDNS_PHY_DLY_UHS_SDR50 … #define SDHCI_CDNS_PHY_DLY_UHS_DDR50 … #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY … #define SDHCI_CDNS_PHY_DLY_EMMC_SDR … #define SDHCI_CDNS_PHY_DLY_EMMC_DDR … #define SDHCI_CDNS_PHY_DLY_SDCLK … #define SDHCI_CDNS_PHY_DLY_HSMMC … #define SDHCI_CDNS_PHY_DLY_STROBE … /* * The tuned val register is 6 bit-wide, but not the whole of the range is * available. The range 0-42 seems to be available (then 43 wraps around to 0) * but I am not quite sure if it is official. Use only 0 to 39 for safety. */ #define SDHCI_CDNS_MAX_TUNING_LOOP … struct sdhci_cdns_phy_param { … }; struct sdhci_cdns_priv { … }; struct sdhci_cdns_phy_cfg { … }; struct sdhci_cdns_drv_data { … }; static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = …; static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg) { … } static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, u8 addr, u8 data) { … } static unsigned int sdhci_cdns_phy_param_count(struct device_node *np) { … } static void sdhci_cdns_phy_param_parse(struct device_node *np, struct sdhci_cdns_priv *priv) { … } static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv) { … } static void *sdhci_cdns_priv(struct sdhci_host *host) { … } static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host) { … } static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode) { … } static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) { … } static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) { … } /* * In SD mode, software must not use the hardware tuning and instead perform * an almost identical procedure to eMMC. */ static int sdhci_cdns_execute_tuning(struct sdhci_host *host, u32 opcode) { … } static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { … } /* Elba control register bits [6:3] are byte-lane enables */ #define ELBA_BYTE_ENABLE_MASK(x) … /* * The Pensando Elba SoC explicitly controls byte-lane enabling on writes * which includes writes to the HRS registers. The write lock (wrlock) * is used to ensure byte-lane enable, using write control (ctl_addr), * occurs before the data write. */ static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg) { … } static void elba_write_l(struct sdhci_host *host, u32 val, int reg) { … } static void elba_write_w(struct sdhci_host *host, u16 val, int reg) { … } static void elba_write_b(struct sdhci_host *host, u8 val, int reg) { … } static const struct sdhci_ops sdhci_elba_ops = …; static int elba_drv_init(struct platform_device *pdev) { … } static const struct sdhci_ops sdhci_cdns_ops = …; static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = …; static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = …; static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = …; static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) { … } static void sdhci_cdns_mmc_hw_reset(struct mmc_host *mmc) { … } static int sdhci_cdns_probe(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int sdhci_cdns_resume(struct device *dev) { … } #endif static const struct dev_pm_ops sdhci_cdns_pm_ops = …; static const struct of_device_id sdhci_cdns_match[] = …; MODULE_DEVICE_TABLE(of, sdhci_cdns_match); static struct platform_driver sdhci_cdns_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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