linux/drivers/mmc/host/sdhci-tegra.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2010 Google, Inc.
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/iommu.h>
#include <linux/iopoll.h>
#include <linux/ktime.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>

#include <soc/tegra/common.h>

#include "sdhci-cqhci.h"
#include "sdhci-pltfm.h"
#include "cqhci.h"

/* Tegra SDHOST controller vendor register definitions */
#define SDHCI_TEGRA_VENDOR_CLOCK_CTRL
#define SDHCI_CLOCK_CTRL_TAP_MASK
#define SDHCI_CLOCK_CTRL_TAP_SHIFT
#define SDHCI_CLOCK_CTRL_TRIM_MASK
#define SDHCI_CLOCK_CTRL_TRIM_SHIFT
#define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE
#define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE
#define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE

#define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL
#define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE

#define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES
#define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK
#define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT

#define SDHCI_TEGRA_VENDOR_MISC_CTRL
#define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT
#define SDHCI_MISC_CTRL_ENABLE_SDR104
#define SDHCI_MISC_CTRL_ENABLE_SDR50
#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300
#define SDHCI_MISC_CTRL_ENABLE_DDR50

#define SDHCI_TEGRA_VENDOR_DLLCAL_CFG
#define SDHCI_TEGRA_DLLCAL_CALIBRATE

#define SDHCI_TEGRA_VENDOR_DLLCAL_STA
#define SDHCI_TEGRA_DLLCAL_STA_ACTIVE

#define SDHCI_VNDR_TUN_CTRL0_0
#define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP
#define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK
#define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT
#define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK
#define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT
#define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK
#define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT
#define TRIES_128
#define TRIES_256
#define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK

#define SDHCI_TEGRA_VNDR_TUN_CTRL1_0
#define SDHCI_TEGRA_VNDR_TUN_STATUS0
#define SDHCI_TEGRA_VNDR_TUN_STATUS1
#define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK
#define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT
#define TUNING_WORD_BIT_SIZE

#define SDHCI_TEGRA_AUTO_CAL_CONFIG
#define SDHCI_AUTO_CAL_START
#define SDHCI_AUTO_CAL_ENABLE
#define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK

#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL
#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK
#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL
#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD
#define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK

#define SDHCI_TEGRA_AUTO_CAL_STATUS
#define SDHCI_TEGRA_AUTO_CAL_ACTIVE

#define SDHCI_TEGRA_CIF2AXI_CTRL_0

#define NVQUIRK_FORCE_SDHCI_SPEC_200
#define NVQUIRK_ENABLE_BLOCK_GAP_DET
#define NVQUIRK_ENABLE_SDHCI_SPEC_300
#define NVQUIRK_ENABLE_SDR50
#define NVQUIRK_ENABLE_SDR104
#define NVQUIRK_ENABLE_DDR50
/*
 * HAS_PADCALIB NVQUIRK is for SoC's supporting auto calibration of pads
 * drive strength.
 */
#define NVQUIRK_HAS_PADCALIB
/*
 * NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads.
 * 3V3/1V8 pad selection happens through pinctrl state selection depending
 * on the signaling mode.
 */
#define NVQUIRK_NEEDS_PAD_CONTROL
#define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP
#define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING

/*
 * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra
 * SDMMC hardware data timeout.
 */
#define NVQUIRK_HAS_TMCLK

#define NVQUIRK_HAS_ANDROID_GPT_SECTOR
#define NVQUIRK_PROGRAM_STREAMID

/* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
#define SDHCI_TEGRA_CQE_BASE_ADDR

#define SDHCI_TEGRA_CQE_TRNS_MODE

struct sdhci_tegra_soc_data {};

/* Magic pull up and pull down pad calibration offsets */
struct sdhci_tegra_autocal_offsets {};

struct sdhci_tegra {};

static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
{}

static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{}

static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{}

static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable)
{}

static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{}

static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
{}

static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host)
{}

static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
{}

static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
{}

static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable)
{}

static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host,
					       u16 pdpu)
{}

static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
				   bool state_drvupdn)
{}

static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
{}

static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
{}

static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{}

static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host)
{}

static void tegra_sdhci_parse_dt(struct sdhci_host *host)
{}

static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{}

static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
					      struct mmc_ios *ios)
{}

static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
{}

static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim)
{}

static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host)
{}

static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up,
				       u8 thd_low, u8 fixed_tap)
{}

static void tegra_sdhci_post_tuning(struct sdhci_host *host)
{}

static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode)
{}

static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
					  unsigned timing)
{}

static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
{}

static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
						   struct mmc_ios *ios)
{}

static int tegra_sdhci_init_pinctrl_info(struct device *dev,
					 struct sdhci_tegra *tegra_host)
{}

static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
{}

static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg)
{}

static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc,
					 struct mmc_request *mrq, u64 *data)
{}

static void sdhci_tegra_cqe_enable(struct mmc_host *mmc)
{}

static void sdhci_tegra_dumpregs(struct mmc_host *mmc)
{}

static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask)
{}

static void tegra_sdhci_set_timeout(struct sdhci_host *host,
				    struct mmc_command *cmd)
{}

static void sdhci_tegra_cqe_pre_enable(struct mmc_host *mmc)
{}

static void sdhci_tegra_cqe_post_disable(struct mmc_host *mmc)
{}

static const struct cqhci_host_ops sdhci_tegra_cqhci_ops =;

static int tegra_sdhci_set_dma_mask(struct sdhci_host *host)
{}

static const struct sdhci_ops tegra_sdhci_ops =;

static const struct sdhci_pltfm_data sdhci_tegra20_pdata =;

static const struct sdhci_tegra_soc_data soc_data_tegra20 =;

static const struct sdhci_pltfm_data sdhci_tegra30_pdata =;

static const struct sdhci_tegra_soc_data soc_data_tegra30 =;

static const struct sdhci_ops tegra114_sdhci_ops =;

static const struct sdhci_pltfm_data sdhci_tegra114_pdata =;

static const struct sdhci_tegra_soc_data soc_data_tegra114 =;

static const struct sdhci_pltfm_data sdhci_tegra124_pdata =;

static const struct sdhci_tegra_soc_data soc_data_tegra124 =;

static const struct sdhci_ops tegra210_sdhci_ops =;

static const struct sdhci_pltfm_data sdhci_tegra210_pdata =;

static const struct sdhci_tegra_soc_data soc_data_tegra210 =;

static const struct sdhci_ops tegra186_sdhci_ops =;

static const struct sdhci_pltfm_data sdhci_tegra186_pdata =;

static const struct sdhci_tegra_soc_data soc_data_tegra186 =;

static const struct sdhci_tegra_soc_data soc_data_tegra194 =;

static const struct sdhci_tegra_soc_data soc_data_tegra234 =;

static const struct of_device_id sdhci_tegra_dt_match[] =;
MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);

static int sdhci_tegra_add_host(struct sdhci_host *host)
{}

/* Program MC streamID for DMA transfers */
static void sdhci_tegra_program_stream_id(struct sdhci_host *host)
{}

static int sdhci_tegra_probe(struct platform_device *pdev)
{}

static void sdhci_tegra_remove(struct platform_device *pdev)
{}

static int __maybe_unused sdhci_tegra_runtime_suspend(struct device *dev)
{}

static int __maybe_unused sdhci_tegra_runtime_resume(struct device *dev)
{}

#ifdef CONFIG_PM_SLEEP
static int sdhci_tegra_suspend(struct device *dev)
{}

static int sdhci_tegra_resume(struct device *dev)
{}
#endif

static const struct dev_pm_ops sdhci_tegra_dev_pm_ops =;

static struct platform_driver sdhci_tegra_driver =;

module_platform_driver();

MODULE_DESCRIPTION();
MODULE_AUTHOR();
MODULE_LICENSE();