// SPDX-License-Identifier: GPL-2.0-or-later /* * drivers/mmc/host/sdhci-of-sparx5.c * * MCHP Sparx5 SoC Secure Digital Host Controller Interface. * * Copyright (c) 2019 Microchip Inc. * * Author: Lars Povlsen <[email protected]> */ #include <linux/sizes.h> #include <linux/delay.h> #include <linux/module.h> #include <linux/regmap.h> #include <linux/mfd/syscon.h> #include <linux/dma-mapping.h> #include <linux/of.h> #include "sdhci-pltfm.h" #define CPU_REGS_GENERAL_CTRL … #define MSHC_DLY_CC_MASK … #define MSHC_DLY_CC_SHIFT … #define MSHC_DLY_CC_MAX … #define CPU_REGS_PROC_CTRL … #define ACP_CACHE_FORCE_ENA … #define ACP_AWCACHE … #define ACP_ARCACHE … #define ACP_CACHE_MASK … #define MSHC2_VERSION … #define MSHC2_TYPE … #define MSHC2_EMMC_CTRL … #define MSHC2_EMMC_CTRL_EMMC_RST_N … #define MSHC2_EMMC_CTRL_IS_EMMC … struct sdhci_sparx5_data { … }; #define BOUNDARY_OK(addr, len) … /* * If DMA addr spans 128MB boundary, we split the DMA transfer into two * so that each DMA transfer doesn't exceed the boundary. */ static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void **desc, dma_addr_t addr, int len, unsigned int cmd) { … } static void sparx5_set_cacheable(struct sdhci_host *host, u32 value) { … } static void sparx5_set_delay(struct sdhci_host *host, u8 value) { … } static void sdhci_sparx5_set_emmc(struct sdhci_host *host) { … } static void sdhci_sparx5_reset_emmc(struct sdhci_host *host) { … } static void sdhci_sparx5_reset(struct sdhci_host *host, u8 mask) { … } static const struct sdhci_ops sdhci_sparx5_ops = …; static const struct sdhci_pltfm_data sdhci_sparx5_pdata = …; static int sdhci_sparx5_probe(struct platform_device *pdev) { … } static const struct of_device_id sdhci_sparx5_of_match[] = …; MODULE_DEVICE_TABLE(of, sdhci_sparx5_of_match); static struct platform_driver sdhci_sparx5_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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