// SPDX-License-Identifier: GPL-2.0-or-later /* * Freescale eSDHC controller driver. * * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. * Copyright (c) 2009 MontaVista Software, Inc. * Copyright 2020 NXP * * Authors: Xiaobo Xie <[email protected]> * Anton Vorontsov <[email protected]> */ #include <linux/err.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/delay.h> #include <linux/module.h> #include <linux/sys_soc.h> #include <linux/clk.h> #include <linux/ktime.h> #include <linux/dma-mapping.h> #include <linux/iopoll.h> #include <linux/mmc/host.h> #include <linux/mmc/mmc.h> #include "sdhci-pltfm.h" #include "sdhci-esdhc.h" #define VENDOR_V_22 … #define VENDOR_V_23 … #define MMC_TIMING_NUM … struct esdhc_clk_fixup { … }; static const struct esdhc_clk_fixup ls1021a_esdhc_clk = …; static const struct esdhc_clk_fixup ls1043a_esdhc_clk = …; static const struct esdhc_clk_fixup ls1046a_esdhc_clk = …; static const struct esdhc_clk_fixup ls1012a_esdhc_clk = …; static const struct esdhc_clk_fixup p1010_esdhc_clk = …; static const struct of_device_id sdhci_esdhc_of_match[] = …; MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); struct sdhci_esdhc { … }; /** * esdhc_readl_fixup - Fixup the value read from incompatible eSDHC register * to make it compatible with SD spec. * * @host: pointer to sdhci_host * @spec_reg: SD spec register address * @value: 32bit eSDHC register value on spec_reg address * * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC * registers are 32 bits. There are differences in register size, register * address, register function, bit position and function between eSDHC spec * and SD spec. * * Return a fixed up register value */ static u32 esdhc_readl_fixup(struct sdhci_host *host, int spec_reg, u32 value) { … } static u16 esdhc_readw_fixup(struct sdhci_host *host, int spec_reg, u32 value) { … } static u8 esdhc_readb_fixup(struct sdhci_host *host, int spec_reg, u32 value) { … } /** * esdhc_writel_fixup - Fixup the SD spec register value so that it could be * written into eSDHC register. * * @host: pointer to sdhci_host * @spec_reg: SD spec register address * @value: 8/16/32bit SD spec register value that would be written * @old_value: 32bit eSDHC register value on spec_reg address * * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC * registers are 32 bits. There are differences in register size, register * address, register function, bit position and function between eSDHC spec * and SD spec. * * Return a fixed up register value */ static u32 esdhc_writel_fixup(struct sdhci_host *host, int spec_reg, u32 value, u32 old_value) { … } static u32 esdhc_writew_fixup(struct sdhci_host *host, int spec_reg, u16 value, u32 old_value) { … } static u32 esdhc_writeb_fixup(struct sdhci_host *host, int spec_reg, u8 value, u32 old_value) { … } static u32 esdhc_be_readl(struct sdhci_host *host, int reg) { … } static u32 esdhc_le_readl(struct sdhci_host *host, int reg) { … } static u16 esdhc_be_readw(struct sdhci_host *host, int reg) { … } static u16 esdhc_le_readw(struct sdhci_host *host, int reg) { … } static u8 esdhc_be_readb(struct sdhci_host *host, int reg) { … } static u8 esdhc_le_readb(struct sdhci_host *host, int reg) { … } static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) { … } static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) { … } static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) { … } static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) { … } static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) { … } static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) { … } /* * For Abort or Suspend after Stop at Block Gap, ignore the ADMA * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) * and Block Gap Event(IRQSTAT[BGE]) are also set. * For Continue, apply soft reset for data(SYSCTL[RSTD]); * and re-issue the entire read transaction from beginning. */ static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) { … } static int esdhc_of_enable_dma(struct sdhci_host *host) { … } static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) { … } static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) { … } static void esdhc_clock_enable(struct sdhci_host *host, bool enable) { … } static void esdhc_flush_async_fifo(struct sdhci_host *host) { … } static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) { … } static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) { … } static void esdhc_reset(struct sdhci_host *host, u8 mask) { … } /* The SCFG, Supplemental Configuration Unit, provides SoC specific * configuration and status registers for the device. There is a * SDHC IO VSEL control register on SCFG for some platforms. It's * used to support SDHC IO voltage switching. */ static const struct of_device_id scfg_device_ids[] = …; /* SDHC IO VSEL control register definition */ #define SCFG_SDHCIOVSELCR … #define SDHCIOVSELCR_TGLEN … #define SDHCIOVSELCR_VSELVAL … #define SDHCIOVSELCR_SDHC_VS … static int esdhc_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) { … } static struct soc_device_attribute soc_tuning_erratum_type1[] = …; static struct soc_device_attribute soc_tuning_erratum_type2[] = …; static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) { … } static void esdhc_tuning_window_ptr(struct sdhci_host *host, u8 *window_start, u8 *window_end) { … } static void esdhc_prepare_sw_tuning(struct sdhci_host *host, u8 *window_start, u8 *window_end) { … } static int esdhc_execute_sw_tuning(struct mmc_host *mmc, u32 opcode, u8 window_start, u8 window_end) { … } static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) { … } static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { … } static u32 esdhc_irq(struct sdhci_host *host, u32 intmask) { … } #ifdef CONFIG_PM_SLEEP static u32 esdhc_proctl; static int esdhc_of_suspend(struct device *dev) { … } static int esdhc_of_resume(struct device *dev) { … } #endif static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, esdhc_of_suspend, esdhc_of_resume); static const struct sdhci_ops sdhci_esdhc_be_ops = …; static const struct sdhci_ops sdhci_esdhc_le_ops = …; static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = …; static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = …; static struct soc_device_attribute soc_incorrect_hostver[] = …; static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = …; static struct soc_device_attribute soc_unreliable_pulse_detection[] = …; static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) { … } static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc) { … } static int sdhci_esdhc_probe(struct platform_device *pdev) { … } static struct platform_driver sdhci_esdhc_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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