// SPDX-License-Identifier: GPL-2.0 /* * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller * * Copyright (C) 2018 Synaptics Incorporated * * Author: Jisheng Zhang <[email protected]> */ #include <linux/acpi.h> #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/dma-mapping.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <linux/sizes.h> #include "sdhci-pltfm.h" #include "cqhci.h" #define SDHCI_DWCMSHC_ARG2_STUFF … /* DWCMSHC specific Mode Select value */ #define DWCMSHC_CTRL_HS400 … /* DWC IP vendor area 1 pointer */ #define DWCMSHC_P_VENDOR_AREA1 … #define DWCMSHC_AREA1_MASK … /* Offset inside the vendor area 1 */ #define DWCMSHC_HOST_CTRL3 … #define DWCMSHC_EMMC_CONTROL … #define DWCMSHC_CARD_IS_EMMC … #define DWCMSHC_ENHANCED_STROBE … #define DWCMSHC_EMMC_ATCTRL … /* Tuning and auto-tuning fields in AT_CTRL_R control register */ #define AT_CTRL_AT_EN … #define AT_CTRL_CI_SEL … #define AT_CTRL_SWIN_TH_EN … #define AT_CTRL_RPT_TUNE_ERR … #define AT_CTRL_SW_TUNE_EN … #define AT_CTRL_WIN_EDGE_SEL_MASK … #define AT_CTRL_WIN_EDGE_SEL … #define AT_CTRL_TUNE_CLK_STOP_EN … #define AT_CTRL_PRE_CHANGE_DLY_MASK … #define AT_CTRL_PRE_CHANGE_DLY … #define AT_CTRL_POST_CHANGE_DLY_MASK … #define AT_CTRL_POST_CHANGE_DLY … #define AT_CTRL_SWIN_TH_VAL_MASK … #define AT_CTRL_SWIN_TH_VAL … /* DWC IP vendor area 2 pointer */ #define DWCMSHC_P_VENDOR_AREA2 … /* Sophgo CV18XX specific Registers */ #define CV18XX_SDHCI_MSHC_CTRL … #define CV18XX_EMMC_FUNC_EN … #define CV18XX_LATANCY_1T … #define CV18XX_SDHCI_PHY_TX_RX_DLY … #define CV18XX_PHY_TX_DLY_MSK … #define CV18XX_PHY_TX_SRC_MSK … #define CV18XX_PHY_TX_SRC_INVERT_CLK_TX … #define CV18XX_PHY_RX_DLY_MSK … #define CV18XX_PHY_RX_SRC_MSK … #define CV18XX_PHY_RX_SRC_INVERT_RX_CLK … #define CV18XX_SDHCI_PHY_CONFIG … #define CV18XX_PHY_TX_BPS … #define CV18XX_TUNE_MAX … #define CV18XX_TUNE_STEP … #define CV18XX_RETRY_TUNING_MAX … /* Rockchip specific Registers */ #define DWCMSHC_EMMC_DLL_CTRL … #define DWCMSHC_EMMC_DLL_RXCLK … #define DWCMSHC_EMMC_DLL_TXCLK … #define DWCMSHC_EMMC_DLL_STRBIN … #define DECMSHC_EMMC_DLL_CMDOUT … #define DWCMSHC_EMMC_DLL_STATUS0 … #define DWCMSHC_EMMC_DLL_START … #define DWCMSHC_EMMC_DLL_LOCKED … #define DWCMSHC_EMMC_DLL_TIMEOUT … #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL … #define DWCMSHC_EMMC_DLL_START_POINT … #define DWCMSHC_EMMC_DLL_INC … #define DWCMSHC_EMMC_DLL_BYPASS … #define DWCMSHC_EMMC_DLL_DLYENA … #define DLL_TXCLK_TAPNUM_DEFAULT … #define DLL_TXCLK_TAPNUM_90_DEGREES … #define DLL_TXCLK_TAPNUM_FROM_SW … #define DLL_STRBIN_TAPNUM_DEFAULT … #define DLL_STRBIN_TAPNUM_FROM_SW … #define DLL_STRBIN_DELAY_NUM_SEL … #define DLL_STRBIN_DELAY_NUM_OFFSET … #define DLL_STRBIN_DELAY_NUM_DEFAULT … #define DLL_RXCLK_NO_INVERTER … #define DLL_RXCLK_INVERTER … #define DLL_CMDOUT_TAPNUM_90_DEGREES … #define DLL_RXCLK_ORI_GATE … #define DLL_CMDOUT_TAPNUM_FROM_SW … #define DLL_CMDOUT_SRC_CLK_NEG … #define DLL_CMDOUT_EN_SRC_CLK_NEG … #define DLL_LOCK_WO_TMOUT(x) … #define RK35xx_MAX_CLKS … /* PHY register area pointer */ #define DWC_MSHC_PTR_PHY_R … /* PHY general configuration */ #define PHY_CNFG_R … #define PHY_CNFG_RSTN_DEASSERT … #define PHY_CNFG_PAD_SP_MASK … #define PHY_CNFG_PAD_SP … #define PHY_CNFG_PAD_SN_MASK … #define PHY_CNFG_PAD_SN … /* PHY command/response pad settings */ #define PHY_CMDPAD_CNFG_R … /* PHY data pad settings */ #define PHY_DATAPAD_CNFG_R … /* PHY clock pad settings */ #define PHY_CLKPAD_CNFG_R … /* PHY strobe pad settings */ #define PHY_STBPAD_CNFG_R … /* PHY reset pad settings */ #define PHY_RSTNPAD_CNFG_R … /* Bitfields are common for all pad settings */ #define PHY_PAD_RXSEL_1V8 … #define PHY_PAD_RXSEL_3V3 … #define PHY_PAD_WEAKPULL_MASK … #define PHY_PAD_WEAKPULL_PULLUP … #define PHY_PAD_WEAKPULL_PULLDOWN … #define PHY_PAD_TXSLEW_CTRL_P_MASK … #define PHY_PAD_TXSLEW_CTRL_P … #define PHY_PAD_TXSLEW_CTRL_N_MASK … #define PHY_PAD_TXSLEW_CTRL_N … /* PHY CLK delay line settings */ #define PHY_SDCLKDL_CNFG_R … #define PHY_SDCLKDL_CNFG_UPDATE … /* PHY CLK delay line delay code */ #define PHY_SDCLKDL_DC_R … #define PHY_SDCLKDL_DC_INITIAL … #define PHY_SDCLKDL_DC_DEFAULT … #define PHY_SDCLKDL_DC_HS400 … /* PHY drift_cclk_rx delay line configuration setting */ #define PHY_ATDL_CNFG_R … #define PHY_ATDL_CNFG_INPSEL_MASK … #define PHY_ATDL_CNFG_INPSEL … /* PHY DLL control settings */ #define PHY_DLL_CTRL_R … #define PHY_DLL_CTRL_DISABLE … #define PHY_DLL_CTRL_ENABLE … /* PHY DLL configuration register 1 */ #define PHY_DLL_CNFG1_R … #define PHY_DLL_CNFG1_SLVDLY_MASK … #define PHY_DLL_CNFG1_SLVDLY … #define PHY_DLL_CNFG1_WAITCYCLE … /* PHY DLL configuration register 2 */ #define PHY_DLL_CNFG2_R … #define PHY_DLL_CNFG2_JUMPSTEP … /* PHY DLL master and slave delay line configuration settings */ #define PHY_DLLDL_CNFG_R … #define PHY_DLLDL_CNFG_SLV_INPSEL_MASK … #define PHY_DLLDL_CNFG_SLV_INPSEL … #define FLAG_IO_FIXED_1V8 … #define BOUNDARY_OK(addr, len) … #define DWCMSHC_SDHCI_CQE_TRNS_MODE … enum dwcmshc_rk_type { … }; struct rk35xx_priv { … }; struct dwcmshc_priv { … }; /* * If DMA addr spans 128MB boundary, we split the DMA transfer into two * so that each DMA transfer doesn't exceed the boundary. */ static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, dma_addr_t addr, int len, unsigned int cmd) { … } static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host) { … } static unsigned int rk35xx_get_max_clock(struct sdhci_host *host) { … } static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, struct mmc_request *mrq) { … } static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq) { … } static void dwcmshc_phy_1_8v_init(struct sdhci_host *host) { … } static void dwcmshc_phy_3_3v_init(struct sdhci_host *host) { … } static void th1520_sdhci_set_phy(struct sdhci_host *host) { … } static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { … } static void th1520_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { … } static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) { … } static int dwcmshc_execute_tuning(struct mmc_host *mmc, u32 opcode) { … } static u32 dwcmshc_cqe_irq_handler(struct sdhci_host *host, u32 intmask) { … } static void dwcmshc_sdhci_cqe_enable(struct mmc_host *mmc) { … } static void dwcmshc_set_tran_desc(struct cqhci_host *cq_host, u8 **desc, dma_addr_t addr, int len, bool end, bool dma64) { … } static void dwcmshc_cqhci_dumpregs(struct mmc_host *mmc) { … } static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) { … } static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) { … } static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) { … } static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask) { … } static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask) { … } static void cv18xx_sdhci_set_tap(struct sdhci_host *host, int tap) { … } static int cv18xx_retry_tuning(struct mmc_host *mmc, u32 opcode, int *cmd_error) { … } static void cv18xx_sdhci_post_tuning(struct sdhci_host *host) { … } static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) { … } static const struct sdhci_ops sdhci_dwcmshc_ops = …; static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = …; static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = …; static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = …; static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = …; #ifdef CONFIG_ACPI static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = …; #endif static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = …; static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = …; static const struct sdhci_pltfm_data sdhci_dwcmshc_cv18xx_pdata = …; static const struct cqhci_host_ops dwcmshc_cqhci_ops = …; static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev) { … } static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) { … } static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) { … } static const struct of_device_id sdhci_dwcmshc_dt_ids[] = …; MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); #ifdef CONFIG_ACPI static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = …; MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids); #endif static int dwcmshc_probe(struct platform_device *pdev) { … } static void dwcmshc_disable_card_clk(struct sdhci_host *host) { … } static void dwcmshc_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int dwcmshc_suspend(struct device *dev) { … } static int dwcmshc_resume(struct device *dev) { … } #endif #ifdef CONFIG_PM static void dwcmshc_enable_card_clk(struct sdhci_host *host) { … } static int dwcmshc_runtime_suspend(struct device *dev) { … } static int dwcmshc_runtime_resume(struct device *dev) { … } #endif static const struct dev_pm_ops dwcmshc_pmops = …; static struct platform_driver sdhci_dwcmshc_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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