/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2016 Marvell, All Rights Reserved. * * Author: Hu Ziji <[email protected]> * Date: 2016-8-24 */ #ifndef SDHCI_XENON_H_ #define SDHCI_XENON_H_ /* Register Offset of Xenon SDHC self-defined register */ #define XENON_SYS_CFG_INFO … #define XENON_SLOT_TYPE_SDIO_SHIFT … #define XENON_NR_SUPPORTED_SLOT_MASK … #define XENON_SYS_OP_CTRL … #define XENON_AUTO_CLKGATE_DISABLE_MASK … #define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT … #define XENON_SLOT_ENABLE_SHIFT … #define XENON_SYS_EXT_OP_CTRL … #define XENON_MASK_CMD_CONFLICT_ERR … #define XENON_SLOT_OP_STATUS_CTRL … #define XENON_TUN_CONSECUTIVE_TIMES_SHIFT … #define XENON_TUN_CONSECUTIVE_TIMES_MASK … #define XENON_TUN_CONSECUTIVE_TIMES … #define XENON_TUNING_STEP_SHIFT … #define XENON_TUNING_STEP_MASK … #define XENON_TUNING_STEP_DIVIDER … #define XENON_SLOT_EMMC_CTRL … #define XENON_ENABLE_RESP_STROBE … #define XENON_ENABLE_DATA_STROBE … #define XENON_SLOT_RETUNING_REQ_CTRL … /* retuning compatible */ #define XENON_RETUNING_COMPATIBLE … #define XENON_SLOT_EXT_PRESENT_STATE … #define XENON_DLL_LOCK_STATE … #define XENON_SLOT_DLL_CUR_DLY_VAL … /* Tuning Parameter */ #define XENON_TMR_RETUN_NO_PRESENT … #define XENON_DEF_TUNING_COUNT … #define XENON_DEFAULT_SDCLK_FREQ … #define XENON_LOWEST_SDCLK_FREQ … /* Xenon specific Mode Select value */ #define XENON_CTRL_HS200 … #define XENON_CTRL_HS400 … enum xenon_variant { … }; struct xenon_priv { … }; int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios); int xenon_phy_parse_params(struct device *dev, struct sdhci_host *host); void xenon_soc_pad_ctrl(struct sdhci_host *host, unsigned char signal_voltage); #endif
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