/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Universal Flash Storage Host controller driver * Copyright (C) 2011-2013 Samsung India Software Operations * * Authors: * Santosh Yaraganavi <[email protected]> * Vinayak Holikatti <[email protected]> */ #ifndef _UFSHCI_H #define _UFSHCI_H #include <linux/types.h> #include <ufs/ufs.h> enum { … }; /* UFSHCI Registers */ enum { … }; /* Controller capability masks */ enum { … }; /* MCQ capability mask */ enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; #define SQ_ICU_ERR_CODE_MASK … #define UFS_MASK(mask, offset) … /* UFS Version 08h */ #define MINOR_VERSION_NUM_MASK … #define MAJOR_VERSION_NUM_MASK … #define UFSHCD_NUM_RESERVED … /* * Controller UFSHCI version * - 2.x and newer use the following scheme: * major << 8 + minor << 4 * - 1.x has been converted to match this in * ufshcd_get_ufs_version() */ static inline u32 ufshci_version(u32 major, u32 minor) { … } /* * HCDDID - Host Controller Identification Descriptor * - Device ID and Device Class 10h */ #define DEVICE_CLASS … #define DEVICE_ID … /* * HCPMID - Host Controller Identification Descriptor * - Product/Manufacturer ID 14h */ #define MANUFACTURE_ID_MASK … #define PRODUCT_ID_MASK … /* AHIT - Auto-Hibernate Idle Timer */ #define UFSHCI_AHIBERN8_TIMER_MASK … #define UFSHCI_AHIBERN8_SCALE_MASK … #define UFSHCI_AHIBERN8_SCALE_FACTOR … #define UFSHCI_AHIBERN8_MAX … /* * IS - Interrupt Status - 20h */ #define UTP_TRANSFER_REQ_COMPL … #define UIC_DME_END_PT_RESET … #define UIC_ERROR … #define UIC_TEST_MODE … #define UIC_POWER_MODE … #define UIC_HIBERNATE_EXIT … #define UIC_HIBERNATE_ENTER … #define UIC_LINK_LOST … #define UIC_LINK_STARTUP … #define UTP_TASK_REQ_COMPL … #define UIC_COMMAND_COMPL … #define DEVICE_FATAL_ERROR … #define CONTROLLER_FATAL_ERROR … #define SYSTEM_BUS_FATAL_ERROR … #define CRYPTO_ENGINE_FATAL_ERROR … #define MCQ_CQ_EVENT_STATUS … #define UFSHCD_UIC_HIBERN8_MASK … #define UFSHCD_UIC_PWR_MASK … #define UFSHCD_UIC_MASK … #define UFSHCD_ERROR_MASK … #define INT_FATAL_ERRORS … /* HCS - Host Controller Status 30h */ #define DEVICE_PRESENT … #define UTP_TRANSFER_REQ_LIST_READY … #define UTP_TASK_REQ_LIST_READY … #define UIC_COMMAND_READY … #define HOST_ERROR_INDICATOR … #define DEVICE_ERROR_INDICATOR … #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK … #define UFSHCD_STATUS_READY … enum { … }; /* HCE - Host Controller Enable 34h */ #define CONTROLLER_ENABLE … #define CONTROLLER_DISABLE … #define CRYPTO_GENERAL_ENABLE … /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */ #define UIC_PHY_ADAPTER_LAYER_ERROR … #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK … #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK … #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR … /* UECDL - Host UIC Error Code Data Link Layer 3Ch */ #define UIC_DATA_LINK_LAYER_ERROR … #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK … #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP … #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP … #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP … #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF … #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT … #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED … #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT … /* UECN - Host UIC Error Code Network Layer 40h */ #define UIC_NETWORK_LAYER_ERROR … #define UIC_NETWORK_LAYER_ERROR_CODE_MASK … #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE … #define UIC_NETWORK_BAD_DEVICEID_ENC … #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING … /* UECT - Host UIC Error Code Transport Layer 44h */ #define UIC_TRANSPORT_LAYER_ERROR … #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK … #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE … #define UIC_TRANSPORT_UNKNOWN_CPORTID … #define UIC_TRANSPORT_NO_CONNECTION_RX … #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING … #define UIC_TRANSPORT_BAD_TC … #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW … #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING … /* UECDME - Host UIC Error Code DME 48h */ #define UIC_DME_ERROR … #define UIC_DME_ERROR_CODE_MASK … /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */ #define INT_AGGR_TIMEOUT_VAL_MASK … #define INT_AGGR_COUNTER_THRESHOLD_MASK … #define INT_AGGR_COUNTER_AND_TIMER_RESET … #define INT_AGGR_STATUS_BIT … #define INT_AGGR_PARAM_WRITE … #define INT_AGGR_ENABLE … /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT … /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ #define UTP_TASK_REQ_LIST_RUN_STOP_BIT … /* REG_UFS_MEM_CFG - Global Config Registers 300h */ #define MCQ_MODE_SELECT … /* CQISy - CQ y Interrupt Status Register */ #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS … /* UICCMD - UIC Command */ #define COMMAND_OPCODE_MASK … #define GEN_SELECTOR_INDEX_MASK … #define MIB_ATTRIBUTE_MASK … #define RESET_LEVEL … #define ATTR_SET_TYPE_MASK … #define CONFIG_RESULT_CODE_MASK … #define GENERIC_ERROR_CODE_MASK … /* GenSelectorIndex calculation macros for M-PHY attributes */ #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) … #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) … #define UIC_ARG_MIB_SEL(attr, sel) … #define UIC_ARG_MIB(attr) … #define UIC_ARG_ATTR_TYPE(t) … #define UIC_GET_ATTR_ID(v) … /* Link Status*/ enum link_status { … }; /* UIC Commands */ enum uic_cmd_dme { … }; /* UIC Config result code / Generic error code */ enum { … }; #define MASK_UIC_COMMAND_RESULT … #define INT_AGGR_COUNTER_THLD_VAL(c) … #define INT_AGGR_TIMEOUT_VAL(t) … /* Interrupt disable masks */ enum { … }; /* CCAP - Crypto Capability 100h */ ufs_crypto_capabilities; enum ufs_crypto_key_size { … }; enum ufs_crypto_alg { … }; /* x-CRYPTOCAP - Crypto Capability X */ ufs_crypto_cap_entry; #define UFS_CRYPTO_CONFIGURATION_ENABLE … #define UFS_CRYPTO_KEY_MAX_SIZE … /* x-CRYPTOCFG - Crypto Configuration X */ ufs_crypto_cfg_entry; /* * Request Descriptor Definitions */ /* To accommodate UFS2.0 required Command type */ enum { … }; enum { … }; /* UTP Transfer Request Data Direction (DD) */ enum utp_data_direction { … }; /* Overall command status values */ enum utp_ocs { … }; enum { … }; /* The maximum length of the data byte count field in the PRDT is 256KB */ #define PRDT_DATA_BYTE_COUNT_MAX … /* The granularity of the data byte count field in the PRDT is 32-bit */ #define PRDT_DATA_BYTE_COUNT_PAD … /** * struct ufshcd_sg_entry - UFSHCI PRD Entry * @addr: Physical address; DW-0 and DW-1. * @reserved: Reserved for future use DW-2 * @size: size of physical segment DW-3 */ struct ufshcd_sg_entry { … }; /** * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD) * @command_upiu: Command UPIU Frame address * @response_upiu: Response UPIU Frame address * @prd_table: Physical Region Descriptor: an array of SG_ALL struct * ufshcd_sg_entry's. Variant-specific fields may be present after each. */ struct utp_transfer_cmd_desc { … }; /** * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD */ struct request_desc_header { … }; static_assert(…); /** * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD) * @header: UTRD header DW-0 to DW-3 * @command_desc_base_addr: UCD base address DW 4-5 * @response_upiu_length: response UPIU length DW-6 * @response_upiu_offset: response UPIU offset DW-6 * @prd_table_length: Physical region descriptor length DW-7 * @prd_table_offset: Physical region descriptor offset DW-7 */ struct utp_transfer_req_desc { … }; /* MCQ Completion Queue Entry */ struct cq_entry { … }; static_assert(…); /* * UTMRD structure. */ struct utp_task_req_desc { … }; #endif /* End of Header */
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